Cisco Technology, Inc.

Robert Leroy King

William Robert Lee

Trevor Garner

Paul Johan Nederveen

John William Marshall

Leo Temoshenko

Kenneth H Potter

Earl Hardin Booth, Iii

John Mitten

Nathan Allen Mitchell

Hugh Nhan

Andrew William Keep

Charles M Parker

Jonathan D Douglas

George R Everhart

Douglas W Currie

In an example, there is disclosed a computing system, including: a processor; a memory; a configuration interface to a logic configuration unit; and a system compiler including: a first block compiler to compile logic for a first logical block in a first language, the first language being a domain-specific language (DSL) and the first logical block being switching logic for a network switch; a second block compiler to compile logic for a second logical block in a second language, the second language being a non-DSL and providing an external accelerator method not supported by the first language; and an interface compiler to define input/output channels for encapsulated data interchange between the first logical block and the second logical block, wherein the encapsulated data interchange is to target a resident instance of the external accelerator method.

Tightly integrated accelerator functions

A technique for use in gathering network activity-related information from network switches is provided. Using this technique, the information can be gathered without substantially reducing performance of the switches. In one embodiment, a single remote monitoring probe is connected by a multiplexer via respective connections to each of the switches so as to receive the information from the switches. In another embodiment, only one of the switches is connected to the probe, and the other switches transmit their respective portions of the information to the switch connected to probe. The switch connected to the probe provides these portions of the information, as well as, any of its respective activity-related information to the probe. In this latter embodiment, the switches may be connected by dedicated connections and switch ports that are used solely for communicating the activity-related information.

Remote monitoring of switch network

A method for communicating in a multi-processor environment is provided that includes generating a bit at an originating processor associated with a message to be communicated to a destination processor. The bit is positioned in a send register associated with the originating processor and transposed from the send register of the originating processor to a receive register of the destination processor. An interrupt signal is then generated in response to the bit being transposed.

System and method for communicating in a multi-processor environment

The present invention provides a system and method for a plurality of independent processors to simultaneously assemble requests in a context memory coupled to a coprocessor. A write manager coupled to the context memory organizes segments received from multiple processors to form requests for the coprocessor. Each received segment indicates a location in the context memory, such as an indexed memory block, where the segment should be stored. Illustratively, the write manager parses the received segments to their appropriate blocks of the context memory, and detects when the last segment for a request has been received. The last segment may be identified according to a predetermined address bit, e.g. an upper order bit, that is set. When the write manager receives the last segment for a request, the write manager (1) finishes assembling the request in a block of the context memory, (2) enqueues an index associated with the memory block in an index FIFO, and (3) sets a valid bit associated with memory block. By setting the valid bit, the write manager prevents newly received segments from overwriting the assembled request that has not yet been forwarded to the coprocessor. When an index reaches the head of the index FIFO, a request is dequeued from the indexed block of the context memory and forwarded to the coprocessor.

Multi processor enqueue packet circuit

In a pipeline network processor, a packet intercept feature determines whether a packet is to be intercepted based on the inbound and outbound port through which the packet travels and based on the source and destination of the packet. When a packet enters the pipeline network processor, a determination is made as to whether the inbound and outbound ports are enabled for packet intercept. If so, a source and/or destination media access control address is compared to a list of configured intercept addresses. If a match is found, a copy of the packet is diverted to an intercept receiver and the original packet is forwarded to its intended destination.

System and method for intercepting packets in a pipeline network processor

A technique for use in gathering network activity-related information from cascaded network switches is provided. Using this technique, the information can be gathered without substantially reducing performance of the cascaded switches. In one embodiment, a single remote monitoring probe is connected via respective connections to each of the switches so as to receive the information from the switches. In another embodiment, only one of the switches is connected to the probe, and the other switches transmit their respective portions of the information to the switch connected to probe. The switch connected to the probe provides these portions of the information, as well as, any of its respective activity-related information to the probe. In this latter embodiment, the switches may be connected by dedicated connections and switch ports that are used solely for communicating the activity-related information.

Growing community of inventors

Raleigh, NC, United States of America

Robert Leroy King