At&t Bell Laboratories

Bell Telephone Laboratories

American Telephone & Telegraph Co., At&t Bell Laboratories

Robert Leonard Pritchett

Peter Theodore Panousis

Adrian R Hartman

Peter W Shackle

John A Carelli, Jr

Richard A Pedersen

Dennis J Lynes

Frederick A D'Altroy

Richard M Jacobs

Peter C Metz

Friedolf Michael Smits

An integrated circuit for detecting harmonic lock of a phase-locked loop includes a frequency synthesizer for receiving a reference clock signal and for generating an oscillator clock signal. A phase generator receives the oscillator clock signal and generates a phase of the oscillator clock signal. A shift register receives as an input the reference clock signal and is clocked by the phase of the oscillator clock signal to produce an output that is a repetitive sequence of logic states. In an alternate embodiment, a harmonic decode circuit decodes the shift register output to determine which harmonic the phase-locked loop has locked onto.

Harmonic lock detector

An integrated circuit for generating an oscillator clock signal based on a reference clock signal includes a wide band digital frequency detector. The wide band digital frequency detector includes a first shift register clocked by the reference clock signal and a second shift register clocked by the oscillator clock signal. A third shift register receives as an input the output from the first shift register and is clocked by the output of the second shift register. The third shift register provides a first oscillator control output. A fourth shift register receives a phase of the reference clock signal as an input and is clocked by the oscillator clock signal to provide a second oscillator control output. In an alternate embodiment, the first oscillator control output is coupled as the up-down control input of an up-down counter and the second oscillator control output is coupled as the clock input to the up-down counter to control the oscillator clock frequency.

Wide range digital frequency detector

Disclosed is an output buffer circuit which converts from CMOS to ECL voltage levels using only CMOS technology. An external resistor provides the buffer with reference voltage levels in combination with a reference circuit. The high and low voltage references are coupled to the gates of separate biasing transistors in separate branches of the buffer circuit. A third transistor controls whether one or both branches will be coupled to the buffer output. In the first case, the low voltage level is established, and in the second case, the high voltage level is set. Additional transistors can be provided to remove charge buildup on the third transistor.

CMOS to ECL output buffer circuit

An integrated circuit includes first and second field effect transistors having differing channel lengths, and a means for comparing the channel currents flowing therethrough. An excessive difference of currents indicates 'short channel' effects, which can degrade performance. A signal flag indicating this condition may be provided to a test pad on the chip, or used to disable operation of the integrated circuit, or otherwise used to provide an indication.

Integrated circuit with channel length indicator

A semiconductor junction-isolated PNPN crosspoint switch array has a plurality of crosspoint switches that are each formed of four regions of alternating conductivity type in a semiconductor substrate. Low enough leakage to allow the crosspoint switch array to be used in large telephone switching systems is achieved by proper selection of the thickness of the semiconductor regions and by appropriate gold doping thereof.

Integrated circuit switching network using low substrate leakage current

A semiconductor read-only-memory (ROM) unit fabricated in large-scale-integrated form utilizing the formation of self-isolating bit-line surface regions of one conductivity type directly in a bulk region of the opposite conductivity type. Channel-stop regions of the same conductivity type as the bulk region are formed in the spaces between bit-line regions. Metallic word-lines overlying and orthogonal to the bit-line regions are formed, separated from the bit-line regions by an insulating layer. The memory cell comprises a single Schottky diode. Such a diode is made or not at each word-line/bit-line crossover location depending respectively on whether or not an aperture is formed in the insulating layer during fabrication to permit the word-line to contact a lightly doped portion of the bit-line. ROM units formed by this method are characterized by small area, high speed, low power dissipation and low cost.

Bipolar read-only-memory unit having self-isolating bit-lines

For identification purposes, a network is added to a multiply configurable microminiature array. During fabrication of the array, the connection pattern of the network is established to be uniquely representative of the particular circuit then being formed in the array. In response to interrogation signals applied to the array, the network provides a unique pattern of voltages representative of the particular circuit. During actual operation of the array, the identification network is in effect automatically disconnected therefrom.

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Bath, PA, United States of America

Robert Leonard Pritchett