Amkor Technology, Inc.

Amkor Technology Singapore Holding Pte. Ltd.

Robert Lanzone

Ludovico Estrada Bancod

Jin Seong Kim

Jae Ung Lee

Yung Woo Lee

Mi Kyeong Choi

Gi Jung Kim

Edwin Joseph Adlam

Sundeep Nand Nangalia

Dean Zehnder

Richard Raymond Green

Glenn A Rinne

Christopher J Berry

Ravi Kiran Chilukuri

Riki Whiting

Rex Beach Anderson, Iii

A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.

Semiconductor package and manufacturing method thereof

Methods for copper pillar protection may include forming a metal post over a contact on a semiconductor die, where the metal post comprises a sidewall. A metal cap may be formed on the metal post and may be wider than the width of the metal post. A solder bump may be formed on the metal cap, and a conformal passivation layer may be formed on at least the sidewall of the metal post. The metal cap may be rounded shaped or rectangular shaped in cross-section. The metal post and the metal cap may comprise copper. The metal cap may comprise a copper layer and a nickel layer. The seed metal layer may comprise one or more of titanium, tungsten, and copper. The conformal passivation layer may comprise a nonwettable polymer. Horizontal portions of the conformal passivation layer may be removed utilizing an anisotropic etch such as a plasma etch.

Copper pillar sidewall protection

An electronic component structure includes a primary redistribution structure having a primary redistribution structure terminal. A secondary redistribution structure is formed on the primary redistribution structure terminal. A buildup dielectric layer encloses the primary redistribution structure, where a cushion pad of the secondary redistribution structure is supported by the buildup dielectric layer. An interconnection ball is mounted to the secondary redistribution structure. Stress imparted upon the interconnection ball is transferred through the secondary redistribution structure and dissipated to the buildup dielectric layer through the cushion pad. The buildup dielectric layer is readily able to absorb this stress thus minimizing the probability of failure of the secondary redistribution structure including the interconnection ball formed thereon.

Electronic component package fabrication method and structure

A bumped substrate is optimized to be flat post reflow. By producing the bumped substrate to be flat post reflow, device reliability is assured. More particularly, the transistor shift associated with warped substrates is avoided. Further, by producing a flat bumped substrate post reflow, reliability in the flip chip interconnections is assured as compared to the undesirable open circuits associated with warped substrates.

Low stress substrate and formation method

A method includes forming a first buildup dielectric layer on a wafer. The wafer includes electronic components delineated from one another by singulation streets. A singulation street exposure light trap layer is formed on the singulation streets. A second buildup dielectric layer is applied and patterned by being selectively exposed to an exposure light. The singulation street exposure light trap layer traps and diffuses the exposure light thus preventing the exposure light from being reflected to the portion of the second buildup dielectric layer above the singulation streets. In this manner, complete removal of the second buildup dielectric layer above the singulation streets is insured.

Electronic component package fabrication method

The present invention is directed to a semiconductor packaging solution wherein a high K thermal material such as a grease or gel is placed in a controlled thin bond line between the semiconductor die of the package and a heat sink in a direct manner using a thermal tape window frame as a low cost mechanical attachment mechanism. As the main thermal dissipation path is between the backside of the semiconductor die and the heat sink, a high K TIM material can be used to maximize thermal dissipation in a manner that does not require expensive mechanical attachment methods.

Semiconductor package thermal tape window frame for heat sink attachment

An electronic component package includes a RDL pattern comprising a redistribution pattern terminal. A buildup dielectric layer is formed on the RDL pattern, the buildup dielectric layer having a redistribution pattern terminal aperture exposing the redistribution pattern terminal. An interconnection ball is formed within the redistribution pattern terminal aperture and on the redistribution pattern terminal. The interconnection ball includes an enclosed portion having an outer concave surface within the buildup dielectric layer. The angle of intersection between the outer concave surface of the interconnection ball and the redistribution pattern is less than 90&#xb0;. This minimizes stress between the interconnection ball and the redistribution pattern which, in turn, minimizes failure of the bond between the interconnection ball and the redistribution pattern.

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Chandler, AZ, United States of America

Robert Lanzone