Advanced Micro Devices Corporation

Robert L Yau

Patrick T Chuang

Ron Maltiel

Moon-Yee Wang

Hiroshi Yoshida

Sinan Doluca

Bill C Tung

Electrical buffer output circuitry includes a first high branch having a high signal input terminal, a low input branch having a low input signal input terminal, and a signal output for the buffer circuitry. Either the high branch or the low branch is turned on in response to a signal at one of the input terminals, and the resistance of the turned on branch is varied as a function of time to improve the speed and noise characteristics of the buffer until the output voltage stabilizes.

Noise reducing output buffer circuit with feedback path

A content addressable memory system includes a plurality of memory cells arranged in rows and columns in an array of N bit words by M word cells, a plurality of word lines extending through the array for addressing different words in the memory cells, each of the words comprising a plurality of adjacent cells extending in a first direction in the array, a plurality of match lines extending through the array in parallel with the word lines in the first direction, a plurality of bit lines extending through the array in a second direction perpendicular to the first direction, each of the bit lines communicating with the cells in one of the columns extending in the second direction, and a pair of registers connected to the bit lines for performing masking operations on bits in the array.

Content addressable memory array with priority encoder

A content addressable memory array includes an array of M words containing bits configured in N bits for each word. One of the bits in each of the words is a settable skip bit, and during a search of the memory array, the array is examined to detect the presence therein of skip bits. If a skip bit is detected in any one of the words, that word containing the detected skip bit is eliminated from the search. Each word in the array also contains an empty bit which is used to indicate an empty word location in the array. When all empty bits are set, the array is automatically reset to empty or zero.

Content addressable memory array with maskable and resettable bits

A content addressable memory system includes an array of memory cells arranged in rows and columns in an array of N bit cells by M words, with N bits per word, an I/O bus having a bit capacity S which is a submultiple of N, a mode generator for generating a plurality of commands, the commands including a command write command, a data write command, a data read command, and a status read command, the command write and the status read commands being encodable in S bits or less, and multiplexing means for supplying selected ones of the commands to the I/O bus.

Content addressable memory array system with multiplexed status and

A capacitor-plate bias generator produces a voltage on the capacitor plate node which consists of a constant voltage plus the sense-level voltage. Consequently, the capacitor-plate node tracks any variations in the sense-level voltage. The constant voltage is 3V.sub.BG, or 3 times the bandgap voltage of silicon. The circuit includes a reference-voltage source which produces the sum of the sense-level voltage and V.sub.BG, and a feedback control circuit for enabling either a charge pump or a charge bleeder to regulate the capacitor-plate voltage at a level above the circuit supply voltage.

Capacitor-plate bias generator for CMOS DRAM memories

Circuitry, including a non-volatile dynamic random access memory cell, a sense amplifier and a data latch affords non-destructive accessing and comparison of the data stored within the volatile and non-volatile portion of the memory cell. In certain applications, it is desirable to restore the volatile data to the volatile portion of the memory cell, and the circuitry also provides a path for such restoration.

Method and apparatus for non-destructive access of volatile and

A memory cell providing separate storage of volatile and non-volatile data. The volatile and non-volatile data elements, which are not necessarily duplicative, can be non-destructively accessed within a single memory clock cycle via separate volatile and non-volatile bit lines. The cell stores volatile data by the storage of charge on a dynamic storage capacitor formed of a semiconductor device and stores non-volatile data by the storage of charge in the floating gate of a transistor. An array of the memory cells illustrates comparison of the volatile and non-volatile data elements within a single memory cycle particularly suited for pattern recognition.

Memory cell providing simultaneous non-destructive access to volatile

A non-volatile dynamic RAM circuit where each memory cell includes an access transistor, a floating gate structure, and a recall transistor connected in series between an I/O bit line and a common line. A conducting plate and storage node of the floating gate structure functions as the volatile storage element of the cell and the floating gate functions as the non-volatile storage element.

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Cupertino, CA, United States of America

Robert L Yau