Micron Technology Incorporated

Robert L Totorica

Charles K Snodgrass

Joseph M Jeddeloh

Michael J Sharpes

John Caldwell

James P Nuxoll

David A Reichle

Charles S Alexander

An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit generates test signals that are applied to the integrated circuit sockets. The integrated test circuit also receives response signals from the integrated circuit sockets indicative of the manner in which integrated circuits in the sockets responded to the test signals. Several of the load boards may be placed on a test head that may be coupled to a host. The integrated test circuit may also be used with an integrated circuit probe card, where the test signals are applied to an integrated circuit coupled to the probe card.

Integrated circuit load board and method having on-board test circuit

A testing method and system is used to test memory modules each of which has a memory hub coupled to a plurality of memory devices. The testing system and method includes a test interface circuit having a memory interface that is coupled to transmit and receive memory signals to and from a tester through a memory bus. The test interface circuit couples test signals to the memory hub in the memory module through a communications link responsive to command, address and data signals received from the tester. The test interface circuit also receives signals from the memory hub in the memory module through the communications link that are indicative of the response of the memory module to the test signals. The test interface circuit then provides corresponding results data to the tester.

Testing system and method for memory modules having a memory hub architecture

An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit generates test signals that are applied to the integrated circuit sockets. The integrated test circuit also receives response signals from the integrated circuit sockets indicative of the manner in which integrated circuits in the sockets responded to the test signals. Several of the load boards may be placed on a test head that may be coupled to a host.

A system allowing testing a plurality of integrated circuits mounted on a common substrate is described. The testing system includes a failure processor mounted on the substrate. The substrate has a first signal port adapted to be coupled to a testing device. The failure processor has a second signal port coupled to the first signal port and a plurality of test ports corresponding in number to the number of integrated circuits mounted on the substrate that are to be tested. Each of the test ports may be coupled to a respective one of the integrated circuits. The failure processor is constructed to apply stimulus signals to each of the integrated circuits and to record response signals generated by each of the integrated circuits in response to the stimulus signals provided to the integrated circuits. The failure processor is further constructed to provide report data based on the response signals and to couple the report data from the second signal port to the first signal port. As a result, many integrated circuits under test may share the first signal port through the failure processor, because the integrated circuits under test are not providing output data on the first signal port to an external test data evaluation apparatus. The efficiency with which integrated circuits may be tested is thereby increased.

On-board testing circuit and method for improving testing of integrated circuits

A wafer cassette includes a stationary dual-zone temperature control base and a removable wafer cassette top. The top includes a main cassette support structure, onto which wafer test electronics, a test interface connector, a wafer interconnect assembly, a wafer test area, a flex film interconnect, and a wafer chuck with evacuation chamber and electric wafer heater, and at least one rough alignment fixture are mounted. A wafer to be tested is inserted, with a pressure-isolating seal, between the wafer chuck and the wafer test area. The base is a stationary fixed portion which includes a first support compartment, a second support compartment and thermal circuits, each of which includes fluid inlet and outlet connections. The fixed portion further includes a heater interconnect to provide connection and external access for a heater element, as well as a vacuum interconnect line to provide external connection to the evacuation chamber. The first and second support compartments are adjacently spaced, and each contains at least one of each of the thermal circuits.

Dual zone wafer test apparatus

A compact and modularly designed apparatus for testing and burning-in semiconductor devices comprises first and second power supplies and the use of direct current (DC) to DC converters. The first power supply provides a high voltage low amperage power source to drive the devices under test (DUTs), and the second power supply supplies 15 volts and 5 volts to drive the circuitry on the testing equipment. The high voltage and low amperage is supplied to slot boards, and the DC to DC converters alter the voltage and current to digital levels. Supplying high voltage and low amperage power through the system to a location electrically near the DUTs, then converting it with DC to DC converters to power the DUTs, allows for much smaller connectors and for a modularly designed burn-in oven.

Modular design for an integrated circuit testing apparatus

The present invention provides for a method and an apparatus for routing electrical signals. The method includes accessing a plurality of electrical circuits. The apparatus includes a supervisory circuit capable of delivering two access signals from a group of first, second, third, and fourth access signals, wherein the supervisory circuit is capable of delivering one of the first and third access signals, and one of the second and fourth access signals. A plurality of electrical circuits is organized into first and second rows. A first portion of the plurality of electrical circuits in the first and second rows, is coupled to a first access signal line. A second portion of the plurality of electrical circuits in the first and second rows is coupled to a second access signal line. The first and second portions of the plurality of electrical circuits in said first row are coupled to a third access signal. The first and second portions of said plurality of electrical circuits in the second row are coupled to a fourth access signal. An access signal is delivered on one of the first and third access signal lines and on one of the second and fourth access signal lines, the electrical circuits being accessed in response to receiving two access signals.

Method and apparatus for signal routing to achieve signal-efficiency

A method and system that uses an anticipatory signal to pre-adjust the output of the power supply to compensate for an upcoming load change, thereby minimizing the voltage deviation at the load. A control circuit, such as a processor, controlling the system generates an anticipatory signal indicating an upcoming change in the load that is input to the power supply. The power supply, in response to the signal from the processor, adjusts the output of the power supply accordingly to compensate for the upcoming load change. When the system performs the operation that results in the load change, the power supply output has already been adjusted accordingly and the deviation of the load voltage caused by the change in the load is minimized.

System with anticipatory power supply load signal

A compact and modularly designed apparatus for testing and burning-in semiconductor devices comprises first and second power supplies and the use of direct current (DC) to DC converters. The first power supply provides high voltage low amperage power to drive the devices under test (DUTs), and the second power supply supplies 15 volts and 5 volts to drive the circuitry on the testing equipment. The high voltage and low amperage is supplied to slot boards, and the DC to DC converters alter the voltage and current to digital levels. Supplying high voltage and low amperage power through the system to a location electrically near the DUTs, then converting it with DC to DC converters to power the DUTs, allows for much smaller connectors and for a modularly designed burn-in oven.

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Boise, ID, United States of America

Robert L Totorica