Honeywell G.m.b.h.

Robert L Spiesman

Tony J Kozlik

David Lyle Kirk

Burke B Baumann

A bidirectional repeater for Manchester encoded data (MED) signals present on a coaxial cable and fiber optic cable forming the transmission media of a local area network. The repeater receives and then reconstitutes the MED signals present on the coaxial cable and transmits the reconstituted MED signals onto the fiber optic cable. MED data present on the fiber optic cable is received, reconstituted, and transmitted onto the coaxial cable. Signals can be received from only one cable at any one time. Transmission of reconstituted MED signals is terminated when a special set of MED signals identifying the end of a transmission by a module of the network is received.

Bidirectional repeater for manchester encoded data signals

A circuit for producing a receive Manchester clock from serially received Manchester encoded data signals. The encoded data signals are differentiated to produce a primary clock pulse for each voltage transition of the applied signals. Each primary clock pulse is delayed a predetermined period of time to produce secondary clock pulse and each secondary clock pulse is delayed for substantially the same period of time to produce a tertiary clock pulse. The primary, secondary and tertiary clock pulses are applied to a gate which produces a receive Manchester clock pulse when a primary, secondary, or tertiary clock pulse is applied to the gate. The frequency of the receive Manchester clock is twice that of the basic frequency of the received Manchester encoded data signals.

Receive Manchester clock circuit

A transceiver for applying signals to and receiving signals from a transmission line through a coupling transformer having a transmission line winding connected to the transmission line and a transceiver winding. A transmitter circuit is connected to the transceiver winding to apply Manchester encoded digital data signals having a high frequency to the transmission line. The transmission line can, at any instant in time, also be carrying data signals which are applied to the transmission line by other transceivers. However, only one transceiver transmits such data signals at any one time. At the same time as the transmission line may be carrying data signals, it can also be carrying timing signals which are applied to it by a timing driver circuit. The timing signals have a significantly lower frequency than the data signals and a quasi-sinusoidal wave form. The transceiver includes a first receiver which is connected across the transceiver winding and which amplifies and reshapes any data signals present across the transceiver winding and produce such signals as the data signal output of the transceiver. A second receiver is also connected across the transceiver winding. This second receiver reconstitutes the received timing signals included in the signals induced or present across the transceiver winding so that the output of the second receiver is a square wave timing signal, the frequency of which is that of the quasi-sinusoidal timing signal received.

Transceiver

A driver circuit for applying a first signal having a desired wave form, frequency and peak to peak voltage to a coaxial transmission line which also has applied to it a second signal having a substantially higher frequency. An operational amplifier has the first signal applied to its noninverting input terminal. The output of the operational amplifier is applied across the primary winding of a driver coupling transformer through an inductor which provides high impedance to the second signal. The voltages induced in the secondary winding of the driver transformer are applied to the transmission line. The primary winding of a feedback transformer is connected in parallel with the secondary winding of the driver transformer. The voltage induced in the secondary winding in the feedback transformer are applied by a feedback circuit including an R.C. filter to the inverting input terminal of the operational amplifier. The signal applied to the inverting input terminal includes both an A.C. component and a D.C. component, which components cause the output current of the operational amplifier to induce in the secondary winding of the driver transformer a signal, the wave form, frequency and peak to peak voltage of which substantially equal those of the first signal applied to the noninverting input terminal of the operational amplifier.

Driver circuit

A method of synchronizing a digital timer with the frequency of a source of A.C. power to provide long term temporal stability. The timer produces internal, fine resolution, synchronization and real time timing signals from a source of clock signals. The periods of all the timer produced timing signals are integral multiples of the period of its internal timing signal. A.C. reference timing signals which are a function of the frequency of the source of A.C. power are applied to the timer. The quotient of the period of the synchronization timing signals by that of the A.C. reference timing signals is an integer 'n'. Once n is determined, the number of fine resolution timing signals in each synchronization period for every n.sup.th A.C. timing signal is compared with a reference value. The timing of the fine resolution timing signals is adjusted to maintain the number of fine resolution timing signals in each synchronization period at which the n.sup.th A.C. reference timing signal is produced substantially equal to the reference value.

Real time clock synchronization

A decoder for Manchester encoded data signals in which the encoded data signals are applied to a first circuit which produces a primary pulse at each voltage transition of the applied signals. The primary pulse enables a delay line oscillator which after a predetermined period of delay produces a decode clock signal of a given frequency. The inverted primary pulse, the decode clock signal, and a constant voltage data input signal are applied to a decoder shift register. The primary pulse and selected outputs of the decoder shift register are applied to a logic circuit which produces a receive clock signal having desired low-to-high voltage transitions occurring substantially in the center of each half-bit cell of a Manchester bit cell. The receive clock signal can be applied to a receive data shift register to which the encoded data signals are also applied so that the binary value of each half-bit cell of a Manchester bit cell can be stored in the data shift register.

Manchester decoder

There is shown a digital output circuit wherein digital data from a computer based controller is applied as input signals to a set of holding latches which are, in turn, enabled by control circuitry such as by response to address signals. The digital data stored in the several holding latches are applied as input signals to a corresponding number of relay driver circuits. The relay driver circuits are, in one aspect of the invention, coupled to selectively operate output control relays in accordance with the data signals applied to the driver circuits therefor. In another form, the driver circuits are connected directly to an output circuit without the intervention of relays. Selective control is provided for establishing the relay output signal in a latched or holding mode or in a controlled time momentary closure mode. In the momentary closure mode the time is established by a data controlled counter. Additionally, a protective circuit is provided which prevents the output circuit from issuing a spurious output signal during a power-up or power-down interval.

Digital output control circuit

An improved multiplexer circuit features an addressing arrangement for effecting the selection, first, of the particular multiplexing module, then of an individual input from among the several inputs to the module. To this end, a latch assembly is provided for storing the address of the individual input to the module. Gating structure is provided, responsive to an address code for enabling the latch assembly to store the applied address code. An output switch is connected in the output circuit of the multiplexer module and operatively controlled by the selecting circuit to block any spurious output from the multiplexer module when the particular multiplexer is not selected.

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Phoenix, AZ, United States of America

Robert L Spiesman