Texas Instruments Corporation

Robert L Pitts

Thomas J Aton

Greg Charles Baldwin

Bryan David Sheffield

Roger Mark Terry

Roger Griesmer

Theodore Warren Houston

Baher S Haroun

Hugh Thomas Mair

Uming U Ko

Vinod J Menezes

Parvinder Kumar Rana

Michael Patrick Clinton

Joe W McPherson

Vijay Kumar Reddy

Alice Wang

Gordon Gammie

David J Toops

Gregory Charles Baldwin

Rashmi Sachan

Andrew M Love

Ramaprasath Vilangudipitchai

Abhishek Kesarwani

Sumanth K Gururjarao

Kun-His Li

Mark J Jensen

Clayton O Timmons

Roger C Griesmer

Integrated circuit () includes substrate () with surface () and structure () including base levels (.(+1)), terminating cells (), and block () of standard cells arranged in rows (.(+1)), and another type of block () outside block (). Standard cells at at least two edges of block () have the following protections: (1) block () has strip of separation () having at least a minimum width from the edges of block (), and protected by one of the following: (2) terminating cells () reduce context effect and some terminating cells () are placed at at least one end of rows (.(+1)) of standard cells within first-named block (), and () the terminating cells () reduce context effect and some terminating cells () are at one end of a column of standard cells within block (). Other structures, devices, and processes are also disclosed.

Integrated circuits and processes for protection of standard cell performance from context effects

Integrated circuit () includes substrate () with surface () and structure () including base levels (.(+1)), terminating cells (), and block () of standard cells arranged in rows (.(+1)), and another type of block () outside block (). Standard cells at at least two edges of block () have the following protections: (1) block () has strip of separation () having at least a minimum width from the edges of block (), and protected by one of the following: (2) terminating cells () reduce context effect and some terminating cells () are placed at at least one end of rows (.(+1)) of standard cells within first-named block (), and (3) the terminating cells () reduce context effect and some terminating cells () are at one end of a column of standard cells within block (). Other structures, devices, and processes are also disclosed.

A memory configurable to be used in an RTA mode includes an input latch configured to receive an input address bus and to generate a latched address bus that corresponds to a memory location. An address flop is configured to save the latched address and to generate a flopped address. A first block address pre-decoder stage is configured to generate a pre-decoded latched address to an RTA generation logic in response to the latched address bus; and a second block address pre-decoder configured to generate a pre-decoded flopped address to the RTA generation logic in response to the flopped address. The RTA generation logic generates an RTA enable signal one clock cycle before a memory block access, to activate a memory block corresponding to the memory location, such that an array supply voltage of the memory block starts charging one clock cycle before a memory block access.

Pseudo retention till access mode enabled memory

A mask build system includes a program for configuring mask layers and a fabrication site for compiling configured mask layers. The system includes at least one database configured by a system processor, the database comprising drawn layers for fabricating reticles of a semiconductor device; and a marker layer configured to define layer dependent features, the marker layer handed off with that part of the at least one database which will support subsequent layers of the database without altering flow of mask build at the fabrication site.

Marker layer to facilitate mask build with interactive layers

Integrated circuit inductors () are formed by interconnecting various metal layers () in an integrated circuit with continuous vias (). Using continuous vias () improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor ().

Integrated circuit inductor with integrated vias

The present invention provides a semiconductor device fuse, comprising a metal layer and a first semiconductor layer that electrically couples the metal layer to a fuse layer, wherein the fuse layer is spaced apart from the metal layer. The semiconductor device fuse further comprises a second semiconductor layer that forms a blow junction interface with the fuse layer. The blow junction interface is configured to form an open circuit when a predefined power is transmitted through the second semiconductor layer to the fuse layer.

Contact fuse which does not touch a metal layer

Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.

Memory power management systems and methods

A logic block, a cell library, a method of designing a logic block and an ASIC including the logic block. The invention provides a logic block including rows of standard cells having different track heights. In one embodiment, the invention provides a logic block including: (1) a first row of standard cells having a first track height and (2) a second row of standard cells adjacent to the first row and having a second track height that differs from the first track height.

Logic block, a multi-track standard cell library, a method of designing a logic block and an asic employing the logic block

Methods are disclosed for the layout and manufacture of microelectronic circuits. The methods employ the monitoring of the placement of macros within circuit layouts for design rule compliance. Upon detection of noncompliance, the macros associated with noncompliance are adapted to bring the layout within the design rules. In a preferred embodiment of the invention monitoring the relative positions of macros includes identifying instances of coinciding macro (x, y) coordinates. Adapting noncompliant macros further includes steps for maintaining minimum (x, y) distances between adjacent macro corners.

Method for generating a mask layout and constructing an integrated circuit

The present invention provides a tunable voltage controller for use with a sub-circuit. In one embodiment, the tunable voltage controller includes a diode-connected MOS transistor contained in a doped well of a substrate and configured to provide a voltage for the sub-circuit. Additionally, the tunable voltage controller also includes a biasing unit configured to adjust the voltage by selectively connecting the doped well to one of a plurality of voltage sources or to a variable voltage source.

Tunable voltage controller for a sub-circuit and method of operating the same

According to one embodiment, a method for isolating degradation mechanisms in transistors includes providing a ring oscillator having a plurality of delay elements. Each delay element operates as a delay element through the use of one or more transistors of only a first type and no transistors of the opposite type. The method further includes operating the ring oscillator and measuring the frequency resulting from the ring oscillator over time. The magnitude of an isolated degradation mechanism is determined based on a comparison of the measured frequency and an expected frequency for the ring oscillator absent degradation.

Method and system for determining transistor degradation mechanisms

An integrated circuit (IC). The integrated circuit comprises an array () of data cells arranged in a plurality of rows and a plurality of columns. Each of the data cells comprises an electrically programmable fuse (), and each electrically programmable fuse comprises a current path for providing a first digital state when the current path is left intact and for providing a second digital state when the current path is destroyed. Each row of the plurality of rows comprises at least one cell reserved for providing a protection indicator for the row, wherein the protection indicator is selected from a set consisting of read protection and write protection. The integrated circuit also comprises control circuitry () for selectively destroying the programmable fuse in selected ones of the data cells in a programmation mode. The integrated circuit also comprises control circuitry () for reading selected ones of the data cells in a read mode.

Integrated circuit with programmable fuse array

This invention describes a means for preventing eFuses from growing back under successive programming pulses after being successfully fused by an earlier set of programming pulses. The solution is achieved through the use of an adaptive programming algorithm for blowing the eFuses. In the adaptive algorithm once a high enough resistance on a blown eFuse has been attained it will not receive additional programming pulses that could cause it to become measurably lower resistance.

Growing community of inventors

Dallas, TX, United States of America

Robert L Pitts