Altera Corporation

Intel Corporation

Xilinx, Inc.

Robert L Pelt

Hong Wang

Arifur Rahman

Ting Lu

Sam Hedinger

Martin Langhammer

Sean R Atsatt

Keone Streicher

Bradley L Taylor

Benjamin J Esposito

Kwan Yee Martin Lee

Balatripura Chavali

Orang Azgomi

James Ryan Kenny

A system for running one or more applications is provided. Each application may require memory services that can be accelerated using configurable memory assistance circuits associated with different levels of a memory hierarchy. Integrated circuit design tools may be used to generate configuration data for programming the configurable memory assistance circuits. During compile time, the design tools may identify memory service patterns in a source code, match the identified memory service patterns to corresponding templates, parameterize the matching templates, and then synthesize the parameterized templates to produce the configuration data. During run time, a memory assistance scheduler may map the memory services required by each application to available memory assistance circuits in the system. The mapped memory assistance circuits are programmed by the configuration data to provide the desired memory service capability.

Circuitry with adaptive memory assistance capabilities

A computer system includes a processor circuit, first and second memory systems, and a configurable memory assistance circuit. The processor circuit is used to run at least one application. The application issues a memory access operation. The configurable memory assistance circuit is in communication with the first and second memory systems and the processor circuit. The configurable memory assistance circuit accelerates the memory access operation for the application using data as the data is in transit between the first and second memory systems.

Techniques for accelerating memory access operations

The present disclosure provides systems and methods for improving provision of secret data on programmable devices. An appliance receives physical unclonable function (PUF) data pertaining to an integrated circuit. Secret data is provided to the appliance from a secret vault. Public and private PUF keys are derived based upon the PUF data. Further, ephemeral public and private keys are derived by the appliance. The public and private PUF keys, along with the ephemeral public and private keys are used to establish a secure channel for programming the secret data on the programmable device.

Programmable device key provisioning

Methods and apparatus relating to diagnostic testing of FPGAs for safety critical systems are described. In an embodiment, logic circuitry (e.g., a processor) performs one or more diagnostic operations on a portion of a Field Programmable Gate Array (FPGA) based on one or more test vectors. Memory stores the one or more test vectors. The logic circuitry performs the one or more diagnostic operations on the portion of the FPGA during runtime. Other embodiments are also disclosed and claimed.

Diagnostic testing of FPGAs for safety critical systems

An integrated circuit (IC) includes a first circuit implemented using programmable circuitry of the IC, and a second circuit implemented using hardened circuitry of the IC. The IC further includes a configurable interface circuit to couple the first circuit to the second circuit using ready/valid signaling with a configurable ready-latency value.

Apparatus for automatically configured interface and associated methods

A bridge circuit may be used to interface between dynamically reconfigurable circuitry and dedicated circuitry or other circuitry having static configurations during normal operation of the device. The bridge circuit may include interface circuitry coupled between first and second interfaces that communicate with the dynamically reconfigurable circuitry and the dedicated circuitry. Control circuitry may control the interface circuitry based on variable communications requirements of the second interface without interrupting communications with the dedicated circuitry at the first interface. The variable communications requirements may be dependent on which configuration of the dynamically reconfigurable circuitry is currently implemented.

Bridge circuitry for communications with dynamically reconfigurable circuits

Methods and systems for AXI ID compression are disclosed. Bus transaction data and an M-bit ID associated with the bus transaction data are transmitted by a master device via a bus to an ID mapper. The ID mapper is used to select, based on the M-bit ID, an N-bit ID from a plurality of N-bit IDs, where N may be less than M. The N-bit ID is associated with the bus transaction data. The bus transaction data and the N-bit ID associated with the bus transaction data are transmitted via the bus to a slave device.

Methods and systems for AXI ID compression

A method of debugging within an integrated circuit (IC) that includes an embedded processor can include detecting an event within a circuit of the IC that is external to the processor and, responsive to detecting the event, initiating a debug function within the processor. Similarly, responsive to detecting an event within the processor, a debug function within a circuit block of the IC that is external to the processor can be initiated. Trace data generated within the processor and trace data generated within the programmable fabric further can be merged to generate combined trace data.

Integrated debugging within an integrated circuit having an embedded processor

A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations, including finite impulse response (FIR) filters and infinite impulse response (IIR) filters. By using the programmable connections, and in some cases the programmable resources of the programmable logic device, and by running portions of the specialized processing block at higher clock speeds than the remainder of the programmable logic device, more complex FIR and IIR filters can be implemented.

Specialized processing block for programmable logic device

A user logic design to hardware application is provided that efficiently implements in a PLD a user logic design multiplier using both programmable logic circuitry and one or more multipliers embedded in DSP circuitry integrated in the PLD. A smaller DSP multiplier may be used by implementing the user logic design multiplier in a sum of partial product arrangement in which one of the partial products is generated using the smaller DSP multiplier with the remaining partial products being generated by multipliers implemented using programmable logic circuitry.

Hybrid multipliers implemented using DSP circuitry and programmable logic circuitry

A polyphase numerically controlled oscillator (PNCO) is defined to include a plurality of sub-numerically controller oscillators (SNCO's). Each SNCO is capable of receiving a clock signal at a first clock rate and an assigned phase offset signal. Each SNCO is configured to generate a digital waveform for the assigned phase offset signal. The PNCO also includes a plurality of frequency multipliers for generating a frequency multiplied representation of the digital waveform generated by each SNCO. The PNCO further includes a multiplexer configured to receive output from each of the frequency multipliers according to the first clock rate. The multiplexer is further configured to receive a select signal, wherein the select signal triggers the multiplexer at a second clock rate.

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San Jose, CA, United States of America

Robert L Pelt