Vlsi Technology, Inc.

Koninklijke Philips Corporation N.V.

Nxp B.v.

Robert L Payne

Martin Harold Manley

Subhas Bothra

Xi-Wei Lin

David R Evoy

Harlan Lee Sur, Jr

Timothy A Pontius

William K Shu

Herbert Reiter

George Ellis Spatz

A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.

Clock domain crossing FIFO

A communication protocol provides high-speed transfers of parallel data between an origination end and a destination end. The protocol involves regularly transmitting data from the origination end to the destination end, including transmitting idle data from the origination end when the destination end is busy and during periods when no commands, data or statuses are pending. When the destination end is not busy, data is sent from the origination end to the destination end by: sequentially transferring read or write commands and, according to a write protocol, pending write data; and transmitting idle packets during periods when no commands are pending. When the origination end is not busy, data is sent from the destination end to the origination end by: sequentially transferring pending end-of-write statuses; sequentially transferring pending read data and read statuses packets according to a read protocol during periods when no end-of-write statuses are pending; and transmitting idle packets during periods when no read data or read status are pending.

High-speed interchip interface protocol

Testing and validation of custom IC designs is performed using standard ICs. Highly complex integrated circuits, instead of being designed at the gates and flops level, are typically designed using standardized cell libraries that allow for widespread, systematic design reuse. Such libraries may include Functional System Blocks, or FSBs (sometimes referred to as ASIC cores), and Application Specific Standard Parts (ASSPs). ASSPs are designs that are or were once realized as stand-alone parts, but that may also be embedded into larger designs (&ldquo;embedded ASSPs&rdquo;). Instead of a conventional software model, testing and validation is performed using a hardware model of a custom integrated circuit. The hardware model may be a breadboard system that is decomposed into three levels of functionality: ASSPs, FSBs and &ldquo;glue logic&rdquo;ASSPs are typically 500K gates or more and may be realized as separate ICs. FSBs are typically 50K gates or less. A collection of commonly used FSBs are therefore provided on a single integrated circuit (FSBIC) in such a way that by applying a predetermined control signal to the FSBIC, it will behave as a selected one of the FSBs. The hardware model may use as many FSBICs as required to map to the FSBs in the custom IC design. Logic on the custom IC that is not part of an ASSP or an FSB may be regarded as glue logic. A hardware emulator (e.g., a programmable logic IC) may be used to model the glue logic.

Custom IC hardware modeling using standard ICs for use in IC design validation

The present invention provides methods and apparatus capable of efficiently combining a logic circuit die with a memory circuit die in a single integrated circuit device capable of supporting memory intensive applications, such as 3-dimensional graphics rendering, encryption and signal processing. The logic circuit die is produced independently with a logic circuit fabrication process that optimizes the logic circuit's performance and reduces costs, and the memory circuit die, which may contain a large memory circuit, can be produced independently with a memory circuit fabrication process that optimizes the memory circuit's performance and reduces costs. The circuit dies are attached directly together in a flip-chip fashion to create a unitary integrated circuit assembly having a high-performance, low impedance, wide-word interface. This integrated circuit assembly can be enclosed within a typical integrated circuit package for insertion on a circuit board, such as those used in personal computers and other common electronic applications.

Face on face flip chip integration

A semiconductor die assembly of this invention includes a lead system in which the leads are arranged in a radial pattern. That is, in a group of leads associated with a single side of a semiconductor die, leads which are furthest from the middle are most angled from the perpendicular. The semiconductor die includes an outer row of bond pads which are located proximate to the edge of the semiconductor die and an inner row of bond pads, parallel to the first row and located toward the interior of the semiconductor die surface. In one embodiment, one of the rows of bond pads is regularly spaced, while the other row of bond pads is variably spaced. The bond pads of the variably spaced row are positioned such that a bond wire which connects a bond pad of the inner row to its associated lead will pass substantially medially between the centers of the two closest bond pads of the outer

Staggered pad array

A programmable resistor is composed of two layers. A first layer of the programmable resistor has a substantially lower resistance than a second layer of the programmable resistor. The programmable resistor is programmed by placing a signal across the programmable resistor. A resulting current generated by the signal travels in parallel through the first layer of the programmable resistor and the second layer of the programmable resistor. The voltage of the signal is of a sufficient level so that a first portion of the resulting current which travels through the first layer causes a break in the first layer of the programmable resistor. However, the voltage of the signal is not of a sufficient level to allow a second portion of the resulting current which travels through the second layer to cause a break in the second layer of the programmable resistor.

Method for bi-layer programmable resistor

Repair cells for performing metal-only functional repairs in a cell-based circuit layout design are described. The repair cells include a gate array under layer made-up of a group of uncommitted (not interconnected) transistors. A cluster of cells can be placed within the cell-based design in various locations and can be coupled together to form logic function elements. The repair cells can be added to cell-based designs during the metalization processing steps so as to repair/change the cell-based design's function. Furthermore, repair cells can be used as feedthrough cells to facilitate routing in the cell-based circuit layout. In this case, feedthrough cells having gate array underlayers may be arranged in columns or are placed in strategic spots within the layout to facilitate routing.

Cell-based integrated circuit design repair using gate array repair cells

A static, in-circuit programmable memory device is provided where the storage element employed is a bi-layer programmable resistor. A specialized programming and readout circuit is provided for each storage element, allowing a known word-line/bit-line memory architecture (commonly used with fuse type memories) to be adapted to a memory element that conducts in both of two different states. The programming and readout circuit may take the form of a merged bipolar/FET device. A bipolar transistor is used for programming and also provides a diode action to prevent sneak path currents from flowing when a storage element is not selected. The bipolar transistor may be a parasitic bipolar transistor. An FET is used for readout. Storage elements are paired, one storage element of each pair functioning as a reference element. The bit lines of the paired storage elements are connected to a current mirror circuit that effects a comparison between current through the reference element and current through its paired storage element. Reliable readout is thereby attained.

Bi-layer programmable resistor memory

A scalable N-port memory device using as a building block a dual-port memory device core. The dual-port memory has two ports each of which can either serve as a read or a write port. The resulting N-port memory device, besides allowing for design reuse, offers speed, density and cost advantages over conventional N-port memory devices. For example, to realize a 1K word by 128 bit register file memory device having two write ports and either five or six read ports, three dual-port memory device cores are placed in parallel with one another. Each core has separate parallel (dual) read ports. Two write ports are shared in common among all of the cores. The cores are designed to operate at 2X speed, i.e., twice the desired speed of the N-port memory device. A 'cycle' at the N-port memory device is composed of two cycles of the underlying 2X speed devices, typically a read cycle followed by a write cycle. During the write cycle, corresponding locations of each of the device cores are written with identical information. The N-port memory device is well suited for design and layout as a memory compiler providing flexibility in specification of the number of ports, the number of words and the word width.

Scalable N-port memory structures

Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.

Growing community of inventors

San Jose, CA, United States of America

Robert L Payne