At&t Bell Laboratories

Lucent Technologies Inc.

At+t Corp.

Robert L Pawelski

William Andrew Payne, Iii

Marianne F Paker

Gaylord W Richards

Jeffrey A Hiltner

Richard James Kos

A system and method is provided for generating a sequence of phase signals. One of the sequence of phase signals that is most closely aligned with a data packet is selected. The data packet is phase aligned with the selected one of the sequence of phase signals. The phase alignment of the data packet includes the generation of a clock signal in alignment with one of the sequence of phase signals.

System and method for phase recovery in a synchronous communication system

A phase recovery circuit consists of a tapped delay line created by a string of inverters where taps are taken at every other inverter. To initialize the circuit, each tap loads a signal sample into a holding register where the holding register consists of a flip-flop connected to each tap. The flip-flops are loaded by the active edges of the system clock such that each flip-flop contains a sample of data at a given point in time. The sample register delivers the data to a processor that periodically creates histograms of the signal to determine the signal transition points between adjacent bits and the number of taps between the transition points that define a bit. Once the transition points are known, the center of the bit to be latched is located and the tap nearest the center of the bit is used to latch the data for delivery to the next downstream location. From the histograms the processor can also determine if the signal is shifting relative to the system clock. If the signal shifts, the processor selects another tap, located nearest the new location of the center of the bit, and latches the data from the new tap. The system also uses an elastic store downstream from the tapped delay line to preclude the need for an extremely long delay time which would cause signal degradation

Phase recovery circuit for high speed and high density applications

A high speed time multiplexed switch (TMS) fabric unit for use in a telecommunications system having relatively low speed TMS access links. To receive signals from the low speed access links, the TMS fabric unit of the invention consists of a plurality of programmable multiplexers where each programmable multiplexer is connected to a predetermined number, J, of the access links. Each access link carries M time slots where M is a relatively large number, i.e. 100. The programmable multiplexers put the content of the access links onto two high speed links. The speed of the high speed links is at least J times the speed of the access links such that for each time slot on the access links there is a fixed group of at least J time slots on each high speed link. Each of the two high speed links deliver the signals to at least one high speed TMS fabric where the speed of the high speed links is matched to the reconfiguration rate of the high speed TMS fabric. To transmit signals from the high speed fabric to the low speed access links, the above-described arrangement is essentially duplicated in that two high speed links connect the high speed TMS fabric to programmable demultiplexers. The programmable demultiplexers deliver the content of the fixed group of J time slots on the high speed links to J access links. The TMS fabrics are non-blocking space division switches between the high speed links coming from the programmable multiplexers and the programmable demultiplexers.

Method and apparatus for interfacing low speed access links to a high

To efficiently implement the algorithm for branching each broadcast call as close to the output of a multi-stage switching fabric as possible, the path hunt for a call path is performed by examining the actual contents of control memories that control the switching stages of the switching system, in order to determine whether--and if so, where--the desired call path may be branched from an existing call path inside of the switching system. For efficiency and speed, the examination is performed by monitoring control memory contents being read out for the purpose of controlling the switching stages, and contents of control memories of multiple stages are monitored in parallel using dedicated monitoring hardware. To avoid the need to examine the control memories' contents in order to determine how much of a call path can be torn down without breaking call path segments shared with other existing call paths, separate counts are kept of instances of present use of connections between stages of the switching fabric, which counts are incremented upon creation of any branching paths that use these connections and are decremented upon breaking of any branching paths that use these connections.

Path hunt for efficient broadcast and multicast connections in

A time-division multiplex switch (100) switches a hierarchy of data rates. It sets up higher-rate connections not as a plurality of individual lowest-rate connections but as one or more time slots in each one of a plurality of sequential frames (40, 50) that correspond to that higher rate in each superframe (30). A time-slot-interchange switching element (131, 141 ) of the switch utilizes a plurality of physically or logically distinct double-buffered data memories (301, 302, 303) each corresponding to a different one of the superframe and different-size ones of the frames. Reading and writing of each of the data memories' buffers alternates with the corresponding one of the superframe and different-size frames; reading of a data memory's buffer immediately follows writing of that buffer. Information from all incoming time slots is written into each one of the data memories, but only information corresponding to the data rate of an individual data memory's corresponding frame size is read that data memory into outgoing time slots. A control memory (305) maps memory locations of the data memories to output time slots. A corresponding control architecture in a switching element (1700) of a time-multiplexed switch (120)uses control memory (1701) that maps input ports to time slots of an output port.

Multirate, sonet-ready, switching arrangement

In a time-space-time switching network that provides connections at a hierarchy of data rates, a path-hunt arrangement effects establishment of a switched connection of a given bandwidth as a collection of a plurality of connections of smaller bandwidths of different sizes. Connections are first found at the highest rate of the hierarchy to satisfy as much of the given bandwidth as possible. Then, connections are found at the lower rates to satisfy any remaining unsatisfied bandwidth. The path-hunt uses a hierarchy of status tables, corresponding to the hierarchy of rates, for each time-switching element of the network. The tables have entries that define availability of time slots--representing bandwidth of the tables' corresponding rates--between that time-switching element and a space-switching stage of the network. Connections are provided at the highest rate by finding matching idle time-slot entries in the high rate status tables for the two time-switching elements involved in the connection. Connections are provided at a lower rate by finding matching partially-full time-slot entries in the highest rate status tables for the two time-switching elements and then finding matching idle time-slot entries in the corresponding lower-rate status tables. To maximize path-hunt efficiency while maintaining non-blocking performance, the path-hunt follows a search hierarchy for lower-rate connections that first searches for matching partially-full time-slot entries in higher-rate status tables, and uses idle time-slot entries in higher-rate status tables only as a last resort.

Hierarchical path hunt for multirate connections

A time-division multiplexed circuit switch (100) handles different-size time-division multiplex frames (30, 40, 50) in a single, shared, time-space-time switching fabric. Both time slot interchange stages (131,141) and a time-multiplexed space stage (120) of the switching fabric receive a plurality of overlapping different-size frames in each incoming superframe (30) of a succession of superframes and interleave switching of the different-size frames through the switching fabric to create a succession of outgoing superframes each one of which also has a plurality of the time-division-multiplex frames of different-sizes but from a plurality of incoming superframes. Switching of every individual received frame of any size commences as soon as the entire individual frame is received.

TDM circuit-switching arrangement that handles frames of different sizes

A time-division multiplex switch (100) switches a hierarchy of data rates. It sets up higher-rate connections not as a plurality of individual lowest-rate connections but as one or more time slots in each one of a plurality of sequential frames (40,50) that correspond to that higher rate in each superframe (30). A time-slot-interchange switching element (131,141) of the switch utilizes a plurality of physically or logically distinct double-buffered data memories (301,302,303) each corresponding to a different one of the superframe and different-size ones of the frames. Reading and writing of each of the data memories' buffers alternates with the corresponding one of the superframe and different-size frames; reading of a data memory's buffer immediately follows writing of that buffer. Information from all incoming time slots is written into each one of the data memories, but only information corresponding to the data rate of an individual data memory's corresponding frame size is read from that data memory into outgoing time slots. A control memory (305) maps memory locations of the data memories to output time slots. A corresponding control architecture in a switching element ( 1700) of a time-multiplexed switch (120) uses a control memory (1701) that maps input ports to time slots of an output port.

A non-blocking broadband broadcast time-division switching system (10) comprises a time-slot replication stage (12) followed by a conventional TMS stage (11). The replication stage replaces the TSI stage of conventional switching systems. Time division multiplexed links (16) are connected to inputs of the system. Each input link is connected to the input of a different replicator (14). Each replicator has as many outputs as there are time slots (202) in a frame (201) on an input link. Replicators' outputs are connected each to a different input of the TMS stage. In one embodiment, a replicator generates each time slot of a received frame at a different output and replicates the individual time slot at the individual output during each time-slot interval of a frame interval. In another embodiment, a replicator generates each time slot of a received frame at a different time at each output, thus generating a delayed replica of the received frame at the outputs. In either embodiment, during each time-slot interval, each replicator transmits a frame of different received time slots to the TMS stage.

High-speed time-division switching system

In a high-quality component video digital transmission system (FIGS. 1 and 2), transmitter DPCM encoders (110-112) and corresponding receiver DPCM decoders (210-212) include respective adaptive quantizers (402-502 and 802-902) in which a set of prediction error-representative values is selected by the predicted value of only the one sample currently being encoded or decoded. At each encoder and decoder, the predicted values are quantized by a quantizer selector (406-506 and 807-907) into groups. One group is selected by the predicted value of the current sample. An adaptive quantizer set is then selected by the selected group. The selected set's prediction error-representative values span a range of error values bounded by the maximum and minimum error values possible for any predicted value of the selecting group. Furthermore, the predicted value of each chrominance sample is forced at each chrominance encoder and decoder by a respective limiter (505, 905) to lie within bounds determined by the correspoding luminance sample value (FIGS. 6 and 7). Improvements in image quality thus obtained permit further transmission rate reduction, by using interleaved subsamplers (107-109). At the transmitter, an interpolation selector (113) selects interpolation methods for reconstructing sample values discarded during subsampling on the basis of only luminance signal samples. At the receiver, both luminance and chrominance interpolators (207-209) apply the same method to reconstruct the value of a luminance and a corresponding chrominance discarded sample. These techniques together enable high-quality component video transmissions to proceed over a 45 Mbps link (200).

Growing community of inventors

Lisle, IL, United States of America

Robert L Pawelski