Zitel Corporation

Saxpy Computer Corporation

Robert L Papenberg

Mohammad F Rydhan

Runchan D Yang

Mohamed M Talaat

David H Wotring

Paul Voloshin

Gary R Lang

Mark C Nicely

Joseph E Straub

Rob Schreiber

Joel Mannion

Ronald Leavitt

A fault tolerant clock system is provided by utilizing redundant clocks which are maintained in synchronization, with voting circuit serving to select one of a plurality of matching clock signals for use. A resistor is coupled in series between the crystal and the oscillation circuit in order to establish a desired duty cycle of the clock signal. A series connected diode capacitor network is connected between a node of the oscillator circuit and a power supply in order to ensure initiation of oscillation.

Fault tolerant memory system

A memory system in which fault tolerance is achieved utilizing redundant clocks. The redundant clocks are synchronized, and a voter is used to deselect nonmatching clocks, thereby avoiding clocking errors. A circuit is provided to ensure a nonoscillating clock provides an output level at a desired state. Another circuit is provided to ensure oscillation upon power up.

An alignment system for transferring only system words of a subarray embedded in an array in system memory between system memory and a buffer memory. The alignment system utilizes a parallel bus that transfers W system words per cycle and selects only subarray words for transfer between the system memory and the buffer. Additionally, a sequencer schedules and executes combinations of random and block accesses to mamximize bandwidth.

Data alignment system for random and block transfers of embedded

A block processing computing system includes a decomposition unit, a control circuit, a system memory, a data block path and a block processor. The decomposition unit receives externally-supplied primitive command packets and decomposes the primitive into machine language operations on computational blocks of data. The control circuitry generates control and address signals for performing the machine level operations. The data block path includes alignment circuitry for selecting data from burst-accessed blocks of data and a macropipeline for controllably storing and transferring blocks of data to and from the block processor. The block processor has interchangeable, double-buffered local zone memories and a parallel set of pipelined vector processors for performing block operations on computational blocks of data.

Architecture for block processing computer system

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San Jose, CA, United States of America

Robert L Papenberg