Unisys Corporation

Robert L Noble

Christopher E Smith

Howard J Keller

A method and system for updating the logical address of pointers used by a processor in a paged memory organization. A logical address associative memory provides a cache holding data about a paged segment of data words eliminating the need to fetch the data from main memory. Update index logic and insertion logic operate to update the logical address of an original pointer to indicate the logical next address of new data sought from main memory. The system is specifically designed to expedite the situation where the page referenced by the next address is different from that referenced by the original pointer's address.

System for pointer updating across paged memory

An associative memory system for logical addressing of memory segments using paged memory. The physical address of a targeted data word can be generated in one machine cycle if the segment logical base address and page index of the targeted word resides in an associated set of CAMs and RAMs. If the targeted word's logical base address and page index is not in the set of associated CAMs and RAMs, this information can be acquired at the most optimum rate for enabling data access. This rate may require several clock cycles.

Associative memory system having segment and page descriptor

A system for updating logical address data in pointers used by a processor in a computer system using paged memory. An Actual Segment Descriptor Associative Memory System (ASDAM) provides a dual cache memory for searching page table logical addresses and page index values which can, if available, provide a logical address, via a logical address RAM, to update a pointer in one machine cycle, with a new logical address. If the required data is not available in the dual cache memory, then other circuitry is operative to translate logical addresses into physical addresses permitting rapid access to main memory in order to supply the dual cache memory and logical address RAM with the required data.

Extended address translation system for pointer updating in paged memory

An alternate path selection structure is provided which reduces the effects of aborting an operation. The present invention comprises a structure and method that allows efficient retrieval of alternate paths to pursue in a microcode sequence. The present invention is useful in a computer system having a central processing unit, input/output units and a memory unit, each of which include means for generating condition signals indicative of the current status thereof, wherein the central processing unit includes a microsequencer comprising storage means for storing microinstructions for the central processing unit, the input/output units and the memory unit; means for storing the last microinstruction retrieved from the storage means; means for generating an alternate address to the storage means in response to the condition signals; means for producing an abort signal also in response to the condition signals; and, means for selecting either the microinstruction retrieved from the storage means or the last microinstruction in the means for storing in response to the state of the abort signal.

Multiple alternate path pipelined microsequencer and method for

An address couple associateive memory (ACAM) for a processor in a chip package provides a first address couple (ACL) CAM and a second absolute address list (AAL) CAM. An associated control unit guarantees coherency of word data in a cache RAM and main memory by indicating the invalidity or validity of each location of address data in the first CAM (ACL) and second CAM (AAL). Each loaction of data words in the cache RAM is associated with a corresponding location in the first (ACL) CAM and in the second (AAL) CAM. Address translation is provided in one clock cycle when writing to a location in main memory specified by a logical address couple.

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Lake Elsinore, CA, United States of America

Robert L Noble