Motorola Corporation

Freescale Semiconductor,inc.

Nxp USA, Inc.

Robert L Maziasz

Mohankumar Guruswamy

Srilata Raman

Daniel Wesley Dulitz

Vladimir Pavlovich Rozenfeld

David Theodore Blaauw

Larry G Jones

Venkata K Chiluvuri

Mohan Guruswamy

Mikhail Anatolievich Sotnikov

Iouri G Smirnov

Igor G Topouzov

Kathleen C Yu

Scott Daniel Hector

Joseph W Norton

Savithri Sundareswaran

Alexander Mikhailovich Marchenko

Claudia A Stanley

Patrick James McGuinness

Alexander Leonidovich Kerre

Sergei Victorovich Somov

Alexander V Zhuravlev

Michael Viacheslavovich Golikov

James E Vasck

Andrea Fernandez

Lyudmila Zinchenko

Andrea Berens

Andrei Vladimirovitch Zinchenko

A method for circuit layout migration comprises creating a list of layout components in a source layout; determining a plurality of first groups of layout components being regularly aligned horizontally or vertically; determining first subsets of layout components which each belong to at least two of a respective set of determined first groups; determining a plurality of second groups of layout components, each second group comprising mutually exclusive ones of the first subsets of layout components; determining symmetry axes for pairs of second groups; building a constraint graph of the layout components of the source layout using alignment constraints for the alignment of layout components within each of the second groups and distance constraints for preserving a regularity pattern within each of the second groups and symmetry constraints for the determined symmetry axes for pairs of second groups; and performing constraint-graph-based compaction of the source layout.

Method and control device for circuit layout migration

Hierarchical layout synthesis of complex cells. In some embodiments, a method may include partitioning a cell into a plurality of subcells, where the cell represents a set of electronic components in an integrated circuit; identifying, among the plurality of subcells, a most complex subcell; synthesizing a layout of the most complex subcell for each of one or more side-port configurations; selecting a side-port configuration based upon the layout of the most complex subcell; and synthesizing a layout of one or more of the plurality of subcells neighboring the most complex subcell by propagating one or more constraints associated with the selected side-port configuration.

Synthesis of complex cells

A layout of a standard cell is created by prioritizing routability characteristics of the standard cell layout. The routability characteristics are prioritized so that the characteristics that are more likely to enhance routing efficiency are emphasized in the cell layout. The prioritization of the routability characteristics can be indicated by a set of weights, with each weight in the set indicating the priority of a corresponding routability characteristic of the standard cell layout. The weights can be used to calculate a weighted sum of the routability characteristics of the standard cell, thereby providing a way to efficiently compare the routability of different standard cell layouts.

Cell routability prioritization

An approach is provided in which an enhanced routing module creates connection objects on a double patterning layout that are correct-by-construction and do not require a semiconductor fabrication stitching process. The enhanced routing module efficiently tracks accumulated mask selection constraints, during maze expansion, when the enhanced routing module traverses possible connection routes from a source grid point to a target grid point. In turn, the enhanced routing module avoids grid points that impose mask selection constraints that are incompatible with existing mask selection constraints of the possible connection routes. As a result, a connection object created by any one of the possible connection routes can be assigned to a specific mask, thus avoiding stitching process requirements from a semiconductor fabrication facility.

Double patterning aware routing without stitching

A layout tool partially replicates the layout of a base cell to determine the layout for a target cell. The base cell is information representing an arrangement of a set of transistors having an established layout. The target cell is information indicating the desired arrangement of another set of transistors. The layout tool identifies correspondences between subsets of the base cell transistors and subsets of the target cell transistors and replicates the layout of the identified base cell subsets to determine the layout for the identified target cell subsets. In addition, the layout tool can identify base cell subsets that closely match target cell subsets, but for which the layout cannot be exactly replicated because of obstructions in the target cell subsets. For such identified base cell subsets, the layout tool can determine a layout by adjusting the base cell subset layouts to avoid the obstructions.

Transistor-level layout synthesis

Embodiments of systems and methods for leakage reduction of a cell are presented herein. According to one embodiment, a path module can identify each rail-to-rail path in a cell. In the embodiment, a transistor set module can select one or more transistors that are coupled to a rail of the cell and, if removed, no rail-to-rail path would exist in the cell. A layout modification module can transform the cell by upsizing a gate length of each transistor of the selected transistors to create a low-leakage version of the cell.

Reducing leakage in standard cells

A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block.

Method of area compaction for integrated circuit layout design

A method, data processing system, and computer program product are provided for routing a circuit placement a number of times, resulting in a number of routings. An electromigration quality value is computed for each of the routings, and the routing with the best electromigration quality value is selected. In one embodiment, each routing is analyzed with attention to the current that passes through each of the routing's segments in order to compute a current distribution that is used to compute a routing quality vector. In another embodiment, multiple placements are generated and the electromigration placement quality vectors are computed for the various placements with the placement with the best electromigration quality vector being selected. In one embodiment, the placement with the best electromigration quality vector is routed the number of times to determine the routing with the lowest (best) electromigration quality value.

System and method for electromigration tolerant cell synthesis

A method for generating an integrated circuit layout is disclosed. One embodiment includes receiving an integrated circuit netlist describing a plurality of transistors and a plurality of conductors for interconnecting the plurality of transistors, each of the plurality of transistors having a width in a layout corresponding to the integrated circuit netlist. More than one of the plurality of transistors are determined to be the widest transistors, all having the same width. One of the widest transistors is folded to produce a folded transistor that is electrically equivalent to the widest transistor. The folded transistor has at least two fingers, each finger having a smaller width than the width of the widest transistors. A fold solution for the layout having the one folded transistor is created.

Method for automated transistor folding

A method of automatically placing transistors of a folded transistor circuit for synthesizing rows of transistors in a semiconductor layout (,). First, an initial placement of transistors is generated (,). Next, a candidate move of transistors is selected (,). Then the change in cost of the placement resulting from applying the candidate move is evaluated (,). A decision is made to accept the candidate move based on the evaluation of its cost (,). If accepted, the move is performed (,) and the cost of the placement is updated (,). Finally, a decision to terminate the process is made (,).

Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors

A method for optimizing contact pin placement in an integrated circuit, wherein a netlist containing connectivity information, and placement information for a semiconductor circuit is read. Each net in the circuit is classified (510). Unblocked tracks are identified for each net in the circuit (512). All contact pins associated with nets having a power supply classification are placed according to a power supply location (513). The blockage for each remaining net is updated. Next, all contact pins for nets residing within a defined diffusion are placed (514) The blockage for each remaining net is updated. Next, all contact pins for nets residing in multiple defined diffusion areas are placed (515).

Method for optimizing contact pin placement in an integrated circuit

A method for automatically selecting tie styles used during the horizontal placement of substrate and well ties. A linear order of tie styles is determined (2422). Ties are placed horizontally in the layout based upon an initial tie style (2424). Route and compact layout components (2426). If the layout has satisfied the tie coverage rules (2428) the tie style selection process is complete. Otherwise, contacts, vias and ties are added where possible (2430). If the layout has now satisfied the tie coverage rules (2432) tie style selection process is complete. If not, the next tie style is chosen from the linear order (2434). The process continues by placing (2424), routing and compacting components (2426) with the new tie style, until the cell satisfies the tie coverage rules.

Method of routing an integrated circuit

A method of interconnecting transistors and other devices in order to optimize area of a layout of a cell while honoring performance constraints (1502) and enhancing yield starts with a prerouting step (152) that routes adjacent transistors using diffusion wiring (1506), routes power and ground nets (1508), routes aligned gates (1510), routes all remaining aligned source/drain nets as well as any special nets (1512). Next, all of the remaining nets are routed using an area based router (1408). Nets are order based on time criticality or net topology (1602). A routing grid is assigned for all the layers to be used in routing (1604). An initial coarse routing is performed (1606). Wire groups are assigned to routing layers (1608). Routing is improved and vias are minimized (1610). A determination is then made whether the routing solution is acceptable (1612). If the routintg solution is not acceptable, the routing space is expanded and routing costs and via costs are modifyied to improve the routing solution. Finally, the best routing solution is picked (1414).

Automatic layout standard cell routing

A method for automatically synthesizing standard cell layouts(170) given a circuit netlist, a template describing the layout style and a set of process design rules (136) starts by numerating an ordered sequence of physical netlists from the logical netlist(138). Next, a netlist is selected from the ordered sequence of physical netlists (140). Components are placed according to the selected physical netlist (144). The components are routed to implement interconnections specified by the netlist (154). The components are compacted (156). A next netlist is selected from the ordered sequence of physical netlists. The steps of placing, routing and compacting the components are repeated. The layout with the smallest width is selected(166). Finally, ies, contacts and vias are added and notches filled (170) to improve yield and performance of the circuit.

Automatic synthesis of standard cell layouts

Methods (100, 200, 250) and data processing system (300) for automatically placing ties (136, 138, 146, 148) and connection elements within an integrated circuit (120). Integrated circuit dimensions (102), element locations and element dimensions (104), and tie placement rules (106) are received for a particular integrated circuit (120). The quantities are then processed to place ties within the integrated circuit (108). Tie placement rules include tie spacings (164, 166), well edge spacings (162), and diffusion spacings (168) to prevent SCR latch up and gate threshold voltage drift. Tie placement methods (100, 200) automatically place ties within the integrated circuit (120) to comply with tie spacing rules and also consider estimated compactions so that tie numbers are minimized. Associated data processing system (300) and computer readable medium operate in conjunction with the methods of the present invention. A method of making an integrated circuit (350) optimally places ties and connection elements within an integrated circuit design.

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Austin, TX, United States of America

Robert L Maziasz