National Semiconductor Corporation

Robert L Macomber

David James Fensore

Gregory Lewis Dean

Kent Bruce Waterson

James E Schuessler

Synchronization management is provided for a continuous serial data streaming application wherein the serial data stream includes a plurality of consecutive, identical-length segments of consecutive serial data bits. Synchronization management bits are provided in each segment. The synchronization management bits are programmed such that the synchronization management bits contained in first and second adjacent segments of the serial data stream will bear a predetermined relationship to one another. At the receiving end, the synchronization management bits are examined from segment to segment. In this manner, synchronization can be monitored, synchronization loss can be detected, and synchronization recovery can be achieved.

Low overhead, data transparent synchronization of streaming serial data

A method for recovering data includes generating a plurality of out-of-phase clock signals. The method also includes generating samples of an incoming data signal, where a plurality of samples are generated using each of the plurality of clock signals. The method further includes selecting one of the plurality of clock signals and providing the samples generated using the selected clock signal. The incoming data signal may be received over a serial interface that includes a clock line for transporting a main clock signal. The out-of-phase clock signals could be approximately 0&#xb0;, 90&#xb0;, 180&#xb0;, and 270&#xb0; out-of-phase with respect to the main clock signal. The out-of-phase clock signals could be used to clock different registers that sample the incoming data signal. The selected clock signal could be selected by identifying a transition that occurs between samples associated with two of the clock signals and then selecting another of the clock signals.

System and method for read data recovery in a serial interface

A method for dynamically selecting a clock edge for recovering read data received from a slave at a master is provided that includes determining whether an internal clock signal is high when a first bit of read data is received at the master. One of a falling edge and a rising edge of the internal clock signal are selected for recovering the read data based on the determination of whether the internal clock signal is high when the first bit of read data is received at the master.

Method and system for dynamically selecting a clock edge for read data recovery

A method and apparatus for dynamically assigning and enabling a unique functional address for a Universal Serial Bus device. A host assigns the unique functional address during a control transaction. The Universal Serial Bus device disables the default address and enables the unique functional address during a status stage of the control transaction to avoid an error window.

Apparatus and method for initializing a universal serial bus device

A peripheral device and a host device implement a scalar interrupt-acknowledgement system. The peripheral device detects events and increments an unprocessed counter in response to each detected event. The host device processes the events and increments a processed counter in response to each processed event. After a number of events have been processed, the host device transmits the value held by the processed counter to the peripheral device. In response, the peripheral device subtracts the value of the processed counter from the value of the unprocessed counter. The peripheral device asserts an interrupt when events remain to be processed and deasserts the interrupt when all the events have been processed.

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Portland, ME, United States of America

Robert L Macomber