Intel Corporation

Robert L Farrell

Altug Koker

Thomas A Piazza

Zeev Offen

Opher D Kahn

Peter D MacWilliams

Karol A Szerszen

Prasoonkumar Surti

Varghese George

Clair C Webb

Subramaniam M Maiyuran

Eliezer Weissmann

Vasanth Ranganathan

Sanjoy K Mondal

Raymond Scott Tetrick

Jerrold Von Hauck

Ali-Reza Adl-Tabatabai

Tomas G Akenine-Moller

Ronny Ronen

Jon N Hasselgren

Boris Ginzburg

Ariel Berkovits

Alireza Sarabi

Peter L Doyle

Carl Jacob Munkberg

Rajesh Bhikhubhai Patel

Louis A Lippincott

Ashish A Pandya

Belliappa Manavattira Kuttanna

Randy Richard Dunton

Saurabh Sharma

Xia Dai

James Edward Phillips

Leslie E Cline

Bimal Poddar

Kalyan Kumar Bhiravabhatla

Esfir Natanzon

Scott E Siers

Dror Avni

Mitchell Diamond

David B Jackson

Yoav Zach

Ilya Osadchiy

Ki W Yoon

Steven D Kassel

T W Griffith

Michael J Muchnick

Adalberto Golbert

Edwin L Jacks, Jr

Paul A Johnson

Mohammad A Abadallah

Kip A Baumann

Rafi M Saied

Harri Syrja

Itzik Silas

Kevin Rogovin

Himanshu Sanghavi

Sharad Mehrotra

Anan Baransy

Avi Liebermensch

Sudarshan Balachandran

John Beaston

A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

Technique to share information among different cache coherency domains

An apparatus and method are described for performing efficient depth test operations. For example, an apparatus in accordance with one embodiment comprises: a depth cache to store a plurality of cache lines containing depth data to be used for graphics processing operations; depth test logic to determine a current depth test function associated with a read operation and to read a cache line from a depth cache while there are still outstanding writes to the cache line if the read operation and write operation are associated with the same depth test function, the depth test logic to perform a first depth test using the data read from the cache line, the first depth test to fail or pass pixels based on a predicted range of depth values.

Optimized depth buffer cache apparatus and method

In position-only shading, two geometry pipes exist, a trimmed down version called the Cull Pipe and a full version called the Replay Pipe. Thus, the Cull Pipe executes the position shaders in parallel with the main application, but typically generates the critical results much faster as it fetches and shades only the position attribute of the vertices and avoids the rasterization as well as the rendering of pixels for the frame buffer. Furthermore, the Cull Pipe uses these critical results to compute visibility information for all the triangles whether they are culled or not. On the other hand, the Replay Pipe consumes the visibility information to skip the culled triangles and shades only the visible triangles that are finally passed to the rasterization phase. Together the two pipes can hide the long cull runs of discarded triangles and can complete the work faster in some embodiments.

Position-only shading pipeline

One or more apparatus and method for multi-pixel/sample level depth testing in a graphics processor is described. In embodiments, a bounding-box of variable size over which a depth test is to be performed is determined based on the pattern of lit pixels or samples within rasterizer tile. A multi-corner depth test may be performed between a source depth data plane and a destination depth plane within a source depth data bound where destination depth data is continuous within the source data bound. A range-based depth test may be performed in response to the destination data being discontinuous. Source depth data prevailing in the depth test may be stored in a compressed plane equation format in response to the source data being continuous within the source data bound, and may be stored as min/max depth data if discontinuous.

Four corner high performance depth test

By packing the depth data in a way that is independent of the number of samples, so that memory bandwidth is the same regardless of the number of samples, higher numbers of samples per pixel may be used without adversely affecting buffer cost. In some embodiments, the number of pixels per clock in a first level depth test may be increased by operating in the pixel domain, whereas previous solutions operated at the sample level.

Constant buffer size multi-sampled anti-aliasing depth compression

A method and system to facilitate a user level application executing in a first processing unit to enqueue work or task(s) safely for a second processing unit without performing any ring transition. For example, in one embodiment of the invention, the first processing unit executes one or more user level applications, where each user level application has a task to be offloaded to a second processing unit. The first processing unit signals the second processing unit to handle the task from each user level application without performing any ring transition in one embodiment of the invention.

Method and system for safe enqueuing of events

Embodiments of apparatuses, methods, and systems for decoding a virtual machine control structure identification are disclosed. In one embodiment, an apparatus includes a virtual machine control structure to decode a virtual machine control structure identification data. The virtual machine control structure identification data is decoded into an address of a virtual machine control structure field and an offset. The offset is to help identify a micro-operation associated with a virtual machine architecture instruction to be executed.

Virtual machine control structure identification decoder

A platform may comprise a core coherency domain, graphics coherency domain and a non-coherent domain. A graphics acceleration unit (GAU) of the graphics coherency domain may generate data units from an application and the data units may comprise display data units. The GAU may annotate the display data units with an annotation value before flushing the display data units to an on-die cache. The GAU may identify modified display data units among the display data units stored in the on-die cache and issue flush commands to cause flushing of the modified display data units from the on-die cache to a main memory. The display engine of the non-coherent domain may use the modified display data units stored in the main memory to render a display on a display device.

Ensuring coherence between graphics and display domains

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Granite Bay, CA, United States of America

Robert L Farrell