International Business Machines Corporation

Zeon Corporation

Globalfoundries Inc.

Macronix International Co., Ltd.

Ulvac, Inc.

Elpis Technologies Inc.

Robert L Bruce

Hiroyuki Miyazoe

Eric Andrew Joseph

Matthew Joseph BrightSky

Joshua T Smith

Sebastian Ulrich Engelmann

Gregory M Fritz

Fabio Carta

Takashi Ando

Chung H Lam

Willi Volksen

Teddie Peregrino Magbitang

Yann A Astier

Cheng-Wei Cheng

Masahiro Nakamura

Sufi Zafar

Benjamin H Wunsch

Takeshi Masuda

Wanki Kim

Payel Das

Takefumi Suzuki

Mahmoud M Khojasteh

John Rozen

Hsinyu Tsai

Joe Lee

Chao Wang

Geraud J Dubois

George Gabriel Totir

HsinYu Tsai

John M Papalia

Theo J Frot

Alexander Reznicek

Ghavam G Shahidi

Bahman Hekmatshoartabari

Guy M Cohen

Kevin K Chan

Cyril Cabral, Jr

Injo Ok

Kenneth Parker Rodbell

Yann Mignot

Chi-Chun Liu

Tymon Barwicz

Yu Zhu

Nelson M Felix

Markus Brink

Kevin W Brew

Nicole A Saulnier

Michael F Lofaro

Nicholas C M Fuller

Aaron Daniel Franklin

Nanbo Gong

Hongwen Yan

Jingwei Bai

Satyavolu S Papa Rao

SangBum Kim

Geraud Jean-Michel Dubois

Iqbal Rashid Saraf

Swetha Kamlapurkar

Jyotica V Patel

Bassem M Hamieh

Bang N To

Gloria Wing Yun Fraczak

Matthew Joseph Brightsky

Alfred Grill

Sampath Purushothaman

Praneet Adusumilli

Qinghuang Lin

Jeng-Bang Yau

Martin Michael Frank

Dirk Pfeiffer

Renee Tong Mo

Satyanarayana Venkata Nitta

Deborah A Neumayer

Dario Leonardo Goldfarb

David Lee Rath

John Christopher Arnold

Nathan P Marchack

Mahadevaiyer Krishnan

Philip Joseph Oldiges

Alshakim Nelson

Jeffrey C Shearer

Lynne Marie Gignac

Jin Ping Han

John C Collins

Huai-Yu Cheng

Koukou Suu

Marinus Hopstaken

Ching-Tzu Chen

Kumar R Virwani

Krystelle Lionti

Asit Kumar Ray

I-Ting Kuo

Norma Edith Sosa

Jitendra Singh Rathore

Masahiro Yamazaki

Adele L Pacquette

Gloria W Fraczak

Gloria W Y Fraczak

Thitima Suwannasiri

Christopher Scerbo

Techniques regarding microfluidic chips with one or more vias filled with sacrificial plugs and/or manufacturing methods thereof are provided herein. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a silicon device layer of a microfluidic chip comprising a plurality of vias extending through the silicon device layer. The plurality of vias comprise greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer. Additionally, the apparatus can comprise a plurality of sacrificial plugs positioned in the plurality of vias.

Microfluidic chips with one or more vias filled with sacrificial plugs

A bottom electrode is deposited on a substrate. A dielectric layer is deposited on the bottom electrode. One or more structures are patterned within the dielectric layer. A liner layer is deposited on top of the dielectric layer and the bottom electrode. A selectivity promotion layer is deposited on top of the liner layer. The selectivity promotion layer is etched to expose a top surface of the dielectric layer and a portion of the bottom electrode. A phase change memory material layer is deposited within a void of the one or more structures between the selectivity promotion layer.

Suppression of void-formation of PCM materials

An electronic device includes a first electrode, a second electrode, and a memory component configured to store a resistive state. The memory component includes a layered region arranged in direct contact with the first electrode and a bulk region arranged in direct contact with the second electrode. The layered region includes a plurality of first layers made of a first material and a plurality of second layers made of a second material alternatingly arranged with one another. The first material is a phase-change material and the second material is a non-phase-change material. The bulk region is a continuous mass made of a third material that is different than the first material and the second material, and the bulk region is in direct contact with at least two of the first layers and at least one of the second layers of the layered region.

Phase-change memory cell with mixed-material switchable region

A process of improving a profile and repairing sidewall damage for phase change memory devices. The process includes applying inert ion beam etching to trim a sidewall of a layer of phase change memory material in a phase change memory device, where the sidewall has been damaged in reactive ion etching using halogens. In the process, the inert ion beam etching is with low energy. In the process, applying the inert ion beam etching to trim the sidewall is at a predetermined low temperature. In the process, applying the inert ion beam etching to trim the sidewall is at a predetermined small angle between an inert ion beam and a surface tangent of the sidewall.

Applying inert ion beam etching for improving a profile and repairing sidewall damage for phase change memory devices

A method for manufacturing a phase-change memory device includes providing a substrate including a plurality of bottom electrodes, patterning the substrate to form a plurality of pores in the substrate extending from a surface of the substrate to the bottom electrodes, depositing a phase-change material over the substrate, implanting one or more of a Ge, Sb and Te in the phase-change material to amorphize at least a portion of the phase-change material inside the pore, planarizing the device to exposed the surface of the substrate, and forming a plurality of top electrodes over the pores, in contact with the phase-change material.

Fill-in confined cell PCM devices

A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.

Integration of selector on confined phase change memory

A phase change memory cell for a semiconductor device that includes a heater element on a first conductive layer with a spacer surrounding sides of the heater element. The phase change memory cell includes a first dielectric layer on the conductive layer and on a bottom portion of the spacer surrounding the heater element and a second dielectric layer on the first dielectric layer surrounding a top portion of the heater element. The phase change memory cell includes a phase change material on a top surface of the heater element and on the second dielectric material.

Embedded heater in a phase change memory material

A structure including a bottom electrode, a phase change material layer vertically aligned and an ovonic threshold switching layer vertically aligned above the phase change material layer. A structure including a bottom electrode, a phase change material layer and an ovonic threshold switching layer vertically aligned above the phase change material layer, and a first barrier layer physically separating the ovonic threshold switching layer from a top electrode. A method including forming a structure including a liner vertically aligned above a first barrier layer, the first barrier layer vertically aligned above a phase change material layer, the phase change material layer vertically aligned above a bottom electrode, forming a dielectric surrounding the structure, and forming an ovonic threshold switching layer on the first barrier layer, vertical side surfaces of the first buffer layer are vertically aligned with the first buffer layer, the phase change material layer and the bottom electrode.

Phase change memory cell with ovonic threshold switch

A method for mitigating moisture driven degradation of silicon doped chalcogenides includes placing a silicon doped chalcogenide composition in a process chamber, passivating dangling silicon bonds of the silicon doped chalcogenide composition by flooding the process chamber with forming gas or with hydrogen plasma, purging the forming gas or the hydrogen plasma from the process chamber, and removing the passivated silicon doped chalcogenide composition from the process chamber.

Mitigating moisture driven degradation of silicon doped chalcogenides

Aspects of the present invention provide a semiconductor structure for a phase change memory device that includes a heater element on a bottom electrode that is surrounded by a dielectric material. The phase change memory device includes a metal nitride liner over the heater element, where the metal liner is oxide-free with a desired electrical resistance. The phase change memory device includes a phase change material is over the heater element and the dielectric material and a top electrode is over the phase change material.

Reactivation of a deposited metal liner

A mushroom type phase change memory (PCM) cell includes a projection liner located between a PCM volume and a bottom electrode. The projection liner has been retained from a layer previously utilized as an etch stop layer during the fabrication of PCM cell and/or the fabrication of the higher level IC device. The projection liner may extend beyond the PCM sidewall(s) or side boundary. This section of the projection liner may be located or buried under a dielectric or an encapsulation spacer and may increase thickness uniformity of the projection liner below the PCM volume.

Integrated phase change memory cell projection liner and etch stop layer

A cross-point memory array and stacked memory array structure. The memory array includes a plurality of first conductive line structures formed in a dielectric material layer; a plurality of memory elements, each memory element including a fill-in phase change memory (PCM) cell, and an access device enabling read or write access to said memory PCM structure; a plurality of second conductive line structures, the plurality of second conductive structures perpendicularly oriented relative to the plurality of first conductive structures. An individual memory element of the plurality of memory elements is conductively connected at a respective intersection between a first conductive line structure and a second conductive line structure. Each phase change memory (PCM) cell of a memory element at an intersection having a sub-lithographic conductive tuning liner disposed on only one sidewall of the PCM cell. The manufacturing maintains a minimal number of masking and processing steps.

Single-sided liner PCM cell for 3D crossbar PCM memory

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White Plains, NY, United States of America

Robert L Bruce