Fairchild Semiconductor Corporation

Ultratech Stepper, Inc.

Robert L Brown

David A Markle

Michael E Thomas

Hwan J Jeong

David S Pan

Richard B Ward

Mark S Wanta

A substrate alignment and exposure system is disclosed The alignment is performed by capturing an image of the substrate with a pattern recognition system, determining the offset from the alignment and moving the substrate relative to the reticle to be in alignment. A first optical alignment system which captures an image of a position of the substrate off of the primary axis of the exposure optics is used to perform pre-alignment. A second optical alignment system captures an image of the reticle and the substrate through the lens of the exposure optics. The pattern recognition system recognizes the alignment keys on the reticle, alignment targets on the substrate, and computes their positions and displacement from alignment. The relative alignment can be direct or inferred. Any angular and translational misalignment is calculated. The pattern recognition system then moves the substrate to be in alignment with the reticle. In the present invention, any arbitrary feature on the reticle and substrate, including device features or specialized alignment keys and targets used by other exposure systems, can be recognized by the pattern recognition system and used for alignment.

Pattern recognition alignment system

In a process of forming vias for multilevel interconnects used in integrated circuits, a layer of a first metal is formed on a semiconductor substrate. A layer of a second metal is formed on the first metal layer. The second metal layer is etched in a predetermined via pattern with a second etchant which reacts with the second metal and which is substantially unreactive with the first metal. The first metal layer is then etched with a first etchant which reacts with the first metal and which is substantialy unreactive with the second metal or with the semiconductor substrate in order to form a predetermined contacting relationship with the predetermined via pattern. This process may be used to generate second and subsequent levels of vias and interconnects which can be used to contact metal layer at any level directly to the substrate by building via posts from the substrate to any desired metal layer.

Process for forming vias on integrated circuits

Growing community of inventors

Palo Alto, CA, United States of America

Robert L Brown