Apple Inc.

Other

Robert L Bailey

Brian D Howard

Michael F Culbert

Mary B Johnson

Lesley B Wynne

Lesley A Bird

Wendell B Sander

James D Kelly

David Ferguson

Wing Hong Chow

R Steven Smith

Krishna Viswanadham

Mark H Seibert

Michael D Johnson

Stephen J O'Connor

Mike S Hanlon

A method and apparatus for viewing and/or analyzing the operations and logical states of an integrated circuit. The logical state of various flip-flops within the ASIC may be determined at a specified time. The embodiment may store these flip-flop states in a computer-readable data structure, such as a file or database. By repeating this process and incrementing or decrementing the time with each repetition, a more complete picture of the ASIC's operation may be captured. Additionally, the embodiment may graphically display the flip-flop states, for example as a graph or waveform.

Analyzing integrated circuit operations

One embodiment of the present invention provides a system that includes an I/O descriptor cache that is accessed by a bus mastering I/O controller. The I/O descriptor cache stores descriptors that describe data to be transferred during corresponding I/O operations. The system also includes an I/O controller configured to control one or more I/O devices. This I/O controller is configured to access I/O descriptors stored in the I/O descriptor cache without having to access the main memory, thereby conserving I/O bandwidth and power.

I/O descriptor cache for bus mastering I/O controllers

Method and apparatus for analyzing integrated circuit operations

Devices are assigned to different buses at development time as well as dynamically during operation, based on actual performance. At development time, bus assignment can be determined based on experiments and direct observation of how devices behave in various configurations. At run time, load on each bus is preferably measured periodically, and when it is uneven, devices are reallocated to different buses. In an alternative embodiment, a user can specify a preference for using more or fewer buses in order to optimize operation for efficiency or lower power consumption.

Dynamically allocating devices to buses

The device to store, sift and measure flour has a container that is generally rectangular in cross section, and that is relatively tall in relation to its horizontal dimensions. A sifting mechanism divides the container roughly in half vertically, and a measuring mechanism is disposed just below the sifting mechanism. Flour is stored in the upper portion of the container, and sifted and measured flour is received into the lower portion of the container, preferably into a removable drawer.

Device to store, sift and measure flour

A method and an apparatus for rotating images on a computer system is disclosed. The system includes a processor for accessing an image frame buffer using a set of CPU addresses, a memory for storing the frame buffer, a controller for directing the pixel data of the frame buffer to a display device using a set of controller addresses. The two sets of addresses are not necessarily the same. In fact, numerous advantages could be had from manipulating those two sets of addresses resulting in image rotation operations for the display device.

Method and apparatus for display image rotation

Apparatus and techniques for awakening bus circuitry from an inactive state as needed are described. The bus circuitry forms part of a computer system and is placed in the inactive state (i.e., shut down) when not needed so as to conserve power. The bus circuitry is associated with a bus and can be awakened out of the inactive state when certain bus events, including resume, connect or disconnect, occur on the bus. The invention is particularly advantageous for computing devices (e.g., portable computers, desktop computers, server computers) where it is desirous to shut down bus circuitry as well as other circuitry (e.g., microprocessor) when not needed so as to reduce power consumption.

Apparatus and method for awakening bus circuitry from a low power state

Methods and apparatus that provide stable clock generation within a functional integrated circuit are disclosed. The functional integrated circuit provides a function other than clock generation, such as a peripheral or interrupt control. Typically, the clock generation is phase-lock loop (PLL) based. The functional integrated circuit also typically provides power savings modes to conserve power consumption.

Stable clock generation internal to a functional integrated circuit chip

An arbiter arbitrates between PCI agents within an ASIC. The ASIC interfaces with an external PCI bus. In operation, the arbiter receives request signals from the PCI agents, and in response thereto, generates a single external request signal. Once the grant is received by the ASIC, the arbiter will route it to a selected PCI agent. The selected agent then gains access to the PCI bus and all other agents are locked out until the transaction is completed. The arbiter is implemented in such a way that there is a minium delay between the generation of the request by any agent and the request sent out by the ASIC. This is performed by ORing all requests.

PCI device arbiter

A computer system in which interrupt signals are serially transmitted from an input/output (I/O) controller is disclosed. The I/O controller initially receives the interrupt signals and then serially transmits them to an interrupt controller where the received interrupt signals are managed. According to the invention, the sequencing by which the interrupt signals are serially transmitted is controlled such that it largely conforms to the sequencing by which the received interrupt signals are processed at the interrupt controller, thereby controlling and reducing latency. The interrupt controller can be a separate integrated circuit chip or integral to another integrated circuit chip of the computer system.

Method and apparatus for serialized interrupt transmission

A method and an apparatus for interleaving display frame buffers for use by multi-panel display(s) is disclosed. The system provides a data addressing transformation apparatus for converting CPU addresses for pixel positions of the multiple panels of display screen(s) to corresponding memory addresses so as to enable multiple video frame buffers to be interleavably stored in and retrieved from a single video memory system.

Multi-panel video display control addressing of interleaved frame

A method and an apparatus for interleaving display frame buffers is disclosed. The system includes a processor providing CPU addresses for peripheral (access, a display system, a single memory system for storing multiple frame buffers, data buses for transferring image information and a video controller for processing the image information received and for converting CPU addresses into memory addresses for accessing the memory system. The multiple frame buffers stored in the memory system in accordance with the present invention provide either overlay images for a display or separate images for separate displays or both.

Method and apparatus for computer display memory management

An improved ring oscillator in which frequency drift is controlled to provide reasonable accuracy is disclosed. The improved ring oscillator eliminates the frequency drift due processing variances. The ring oscillator provided by the invention incurs substantially less frequency drift than a conventional ring oscillator, but the frequency of the ring oscillator is still dependent on temperature and voltage changes. The improved ring oscillator according to the invention is particularly suited for operating as a localized oscillator that is used to facilitate periodic refreshing of DRAM within a computer.

Growing community of inventors

San Jose, CA, United States of America

Robert L Bailey