International Business Machines Corporation

Robert L Ayers

James Scott Womble

Heidi D Williams

Michael Charles Elles

Tu T Dang

Michael Leo Scollard

Raymond W Hamaker

Ketan B Patel

A robust printed circuit board (PCB) that includes at least two power layers that are used in providing power to components connected to the PCB. The power layers may be a power plane layer and a ground plane layer. The power plane layer is situated such that its edge is pulled back a second distance from the planar edge of the PCB. The ground plane layer is situated such that its edge is pulled back a first distance from the planar edge of the PCB. The second distance and the first distance are different, and as a result, the planar edges of the power plane layer and the ground plane layer respectively do not coincide.

Robust power plane configuration in printed circuit boards

A dual-sided connector pin interposer includes a substrate comprising a first side opposite a second side. The interposer includes a first plurality of flexible pins protruding from the first side of the substrate. The first plurality of flexible pins is positioned for installation in a first plurality of pad connectors of the pinless socket. The interposer includes a second plurality of flexible pins protruding from the second side of the substrate. The second plurality of flexible pins is positioned for installation in a second plurality of pad connectors of the pinless integrated circuit component. The first plurality of flexible pins are electrically connected to the second plurality of flexible pins through the substrate to provide electrical contact points between the pinless socket and the pinless integrated circuit component when the interposer is installed.

Removable and replaceable dual-sided connector pin interposer

Certain types of silicon integrated circuits are embodied as having diffused isolation regions surrounding epitaxial regions. Although normally operated in a reverse bias mode, such regions may become forward biased when sourcing current for certain circuit applications. Certain types of ionized impurities lodged in the isolation region can then migrate into the depletion region and the epitaxial region of the device during a forward bias condition. Such contaminants can be expected to produce generation-recombination centers in the depletion layer of the device which, when the isolation region is then reverse biased, will produce significant increases in junction leakage current. The magnitude of this reverse bias leakage current will depend upon both the contaminant concentration and the width of the depletion region.

Technique for preventing forward biased epi-isolation degradation

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Durham, NC, United States of America

Robert L Ayers