Texas Instruments Corporation

Qorvo Us, Inc.

Texax Instruments Incorporated

Robert Kraft

Ting Yiu Tsui

Ping Jiang

John Belsick

Derya Deniz

Francis Gabriel Celii

Matthew Wasilik

Andrew McKerrow

Satyavolu Srinivas Papa Rao

David Gerald Farber

Kenneth Joseph Newton

Scott Robert Summerfelt

Haowen Bu

Antonio L P Rotondaro

Theodore Sidney Moise

Guoqiang Xing

Kezhakkedath Ramunni Udayakumar

Sunil V Hattangady

Reima Tapani Laaksonen

Hyesook Hong

William Wesley Dostalik

Sanjeev Aggarwal

Ebrahim Andideh

Mark H Somervell

Douglas Ticknor Grider

Wei-Yung Hsu

James Walter Blatchford

Yaw S Obeng

Buu Quoc Diep

Lindsey H Hall

Srikanth Krishnan

Kenneth D Brennan

Dirk N Anderson

Ian Y Yee

Katherine E Violette

Craig Henry Huffman

James B Friedmann

Scott H Prengle

Brian Ashley Smith

Jeff A West

Jeannette Michelle Jacques

Daty Michael Rogers

Laura M Matz

Zhicheng Tang

Rebecca J Gale

Bang Nguyen

Ting Y Tsui

Thad E Briggs

Andrew Ralston

Charlotte M Appel

Brian E Goodllin

A structure includes a substrate including a wafer or a portion thereof; and a piezoelectric bulk material layer comprising a first portion deposited onto the substrate and a second portion deposited onto the first portion, the second portion comprising an outer surface having a surface roughness (Ra) of 4.5 nm or less. Methods for depositing a piezoelectric bulk material layer include depositing a first portion of bulk layer material at a first incidence angle to achieve a predetermined c-axis tilt, and depositing a second portion of the bulk material layer onto the first portion at a second incidence angle that is smaller than the first incidence angle. The second portion has a second c-axis tilt that substantially aligns with the first c-axis tilt.

Piezoelectric bulk layers with tilted c-axis orientation and methods for making the same

Methods for depositing bulk layer crystalline material having a predetermined c-axis tilt on a substrate include a first step of depositing a first portion of bulk layer material at a first incidence angle to achieve a predetermined c-axis tilt, and a second step of depositing a second portion of the bulk material layer onto the first portion at a second incidence angle that is smaller than the first incidence angle. The second portion has a second c-axis tilt that substantially aligns with the first c-axis tilt.

Method for manufacturing piezoelectric bulk layers with tilted c-axis orientation

Bulk acoustic wave resonator structures include a bulk layer with inclined c-axis hexagonal crystal structure piezoelectric material supported by a substrate. The bulk layer may be prepared without first depositing a seed layer on the substrate. The bulk material layer has a c-axis tilt of about 32 degrees or greater. The bulk material layer may exhibit a ratio of shear coupling to longitudinal coupling of 1.25 or greater during excitation. A method for preparing a crystalline bulk layer having a c-axis tilt includes depositing a bulk material layer directly onto a substrate at an off-normal incidence. The deposition conditions may include a pressure of less than 5 mTorr and a deposition angle of about 35 degrees to about 85 degrees.

The present disclosure relates to a Wafer-Level-Packaged (WLP) Bulk Acoustic Wave (BAW) device that includes a BAW resonator, a WLP enclosure, and a surface mount connection structure. The BAW resonator includes a piezoelectric layer with an opening and a bottom electrode lead underneath the piezoelectric layer, such that a portion of the bottom electrode lead is exposed through the opening of the piezoelectric layer. The WLP enclosure includes a cap and an outer wall that extends from the cap toward the piezoelectric layer to form a cavity. The opening of the piezoelectric layer is outside the cavity. The surface mount connection structure covers a portion of a top surface of the cap and extends continuously over a side portion of the WLP enclosure and to the exposed portion of the bottom electrode lead through the opening of the piezoelectric layer.

Wafer-level-packaged BAW devices with surface mount connection structures

A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60&#xb0; C.

Ferroelectric capacitor manufacturing process

The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (). A strain inducing liner is formed over the semiconductor device (). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region ().

Systems and methods that selectively modify liner induced stress

A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.

Method for cleaning post-etch noble metal residues

The present invention provides an interconnect structure, a method of manufacture therefore, and a method for manufacturing an integrated circuit including the same. The method for forming the interconnect structure, among other steps, includes subjecting a first portion () of a substrate () to a first etch process, the first etch process designed to etch at a first entry angle (&#x3b8;), and subjecting a second portion () of the substrate () to a second different etch process, the second different etch process designed to etch at a second lesser entry angle (&#x3b8;).

Method for reducing line edge roughness for conductive features

In accordance with the present teachings, semiconductor devices and methods of making semiconductor devices and dielectric stack in an integrated circuit are provided. The method of forming a dielectric stack in an integrated circuit can include providing a semiconductor structure including one or more copper interconnects and forming an etch stop layer over the semiconductor structure in a first processing chamber. The method can also include forming a thin silicon oxide layer over the etch stop layer in the first processing chamber and forming an ultra low-k dielectric layer over the thin silicon oxide layer in a second processing chamber, wherein forming the thin silicon oxide layer improves adhesion between the etch stop layer and the ultra low-k dielectric as compared to a dielectric stack that is devoid of the thin silicon oxide layer between the etch stop layer and the ultra low-k dielectric.

Formation of a silicon oxide interface layer during silicon carbide etch stop deposition to promote better dielectric stack adhesion

The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an integrated circuit. The process for improving the hardness and/or modulus of elasticity of a dielectric layer, among other steps, includes providing a dielectric layer having a hardness and a modulus of elasticity, and subjecting the dielectric layer to an energy beam, thereby causing the hardness or modulus of elasticity to increase in value.

Energy beam treatment to improve packaging reliability

A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered. A second dielectric layer is formed on the first dielectric layer. An etch rate of the second dielectric layer is then altered. A trench etch is performed to form a trench cavity within the second dielectric layer. A via etch is performed to form a via cavity within the first dielectric layer. The cavities are filled with conductive material and then planarized to remove excess fill material.

Methods to facilitate etch uniformity and selectivity

A method of forming a gate electrode (') for a metal-oxide-semiconductor (MOS) integrated circuit is disclosed. A hardmask layer (), for example formed of silicon-rich nitride, is deposited over a polysilicon layer () from which the gate electrode (&#x2032;) is to be formed. An anti-reflective coating, or bottom anti-reflective coating or BARC, layer () is then formed over the hardmask layer (), and photoresist () is photolithographically patterned to define the pattern of the gate electrode (&#x2032;), although to a wider, photolithographic, width (LW). The pattern is transferred from the photoresist () to the BARC layer (). The remaining elements of the BARC layer () are then trimmed, preferably by a timed isotropic etch, to a sub-lithographic width (SW). This pattern is then transferred to the hardmask layer () by an anisotropic etch of that layer, using the trimmed BARC elements () as a mask. The hardmask layer elements (&#x2032;) then mask the etch of the underlying polysilicon layer (), to define the gate electrodes (&#x2032;), having gate widths that are narrower than the minimum dimension available through photolithography.

Method for patterning sub-lithographic features in semiconductor manufacturing

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Plano, TX, United States of America

Robert Kraft