Amazon Technologies, Inc.

Robert Klein

Darin Lee Frink

Erez Izenberg

Alan Michael Judge

Said Bshara

Barak Wasserstrom

Kevin M Bailey

Ziv Harel

Joshua Benjamin Levinson

Julien Ridoux

Priscilla Lam

Shay Madar

Idan Saar

David Ben-Dror

Charles Caldwell Phares

A hardware card that can be implemented in a server system is disclosed. The hardware card may be, for instance, a network interface card coupled to a board such as a motherboard or backplane in a computing system. In various instances, the hardware card reports a temperature to a management controller on the board (e.g., a baseboard management controller) that is adjusted due to thermal degradation of the hardware card. For example, the temperature output by the hardware card may be adjusted based on a comparison of a current temperature profile (including transient temperature of the hardware card) to a predetermined temperature profile stored on the hardware card.

Dynamic hardware card thermal adaptation

Systems and methods are provided for highly accurate synchronization of machine instances in a distributed, hosted computing environment to a reference timekeeper. In addition to a general communication network accessible to machine instances, the distributed environment includes a second network dedicated to carrying time information, such as a pulse-per-second (PPS) signal to isolated timing hardware within host computing devices. The isolated timing hardware can use the PPS signal, along with a reference time, to set a hardware clock. The isolated timing hardware can further provide an interface to machine instances that enables the instances to read the time of the hardware clock. This configuration enables many instances can share access to a single reference timekeeper, thus synchronizing those instances to a much higher accuracy than in traditional network-based time protocols.

Highly accurate time information in hosted machine instances using dedicated timing network

Approaches in accordance with various embodiments can be used to provide bootstrap data for a computing device, such as a system on chip (SoC). In particular, various embodiments can use one or more shift registers to receive bits of a sequence of bootstrap data in parallel. Individual bits of this bootstrap data sequence can then be provided to the SoC, from the shift register(s), serially and using a single input. Such an approach prevents the need for multiple bootstrap pins on the SoC, as well as the need to multiplex those pins for use with other external devices.

Serial bootstrap

An electrical connection system can include a cage and/or a corresponding cable. The cage can be formed by walls and define faces on the top, bottom, right, left, front, and rear. A rear portion can house a receiving portion of a connector interface, which can be engaged via insertion of a module through the front face, or alternately by insertion of a plug through the top face. The cable at a terminating end can include the plug, which may include a vertical upright column and a horizontal base that includes an insertion portion of the connector interface. The cable at an originating end can include another instance of the receiving portion of the connector interface. A retainer can be provided to retain the plug in engagement with the receiving portion of the connector in the cage. The retainer can include a cover or other structure on the cable and/or cage.

Connector for multiple cabling arrangements

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Kfar Tavor, Israel

Robert Klein