Motorola Corporation

Robert Keith DeHaven

James F Wenzel

Bryan D Marietta

James Patrick Johnston

A method, apparatus, and circuit distribution wafer (CDW) ( ) are used to wafer-level test a product wafer ( ) containing one or more product integrated circuits (ICs). The CDW ( ) contains circuitry which is used to test the ICs on the product wafers ( ). A connection from the product wafer ( ) to the CDW ( ) is made via a compliant interconnect media (IM) ( ). Through IM ( ), the CDW ( ) tests the product wafer ( ) under any set of test conditions. Through external connectors and conductors ( and ) the CDW ( ) transmits and receives test data, control information, temperature control, and the like from an external tester ( ). To improve performance and testability, the CDW ( ) and heating/cooling ( and ) of the wafers may be segmented into two or more wafer sections for greater control and more accurate testing.

Apparatus, method, and wafer used for testing integrated circuits formed on a product wafer

A method, apparatus, and circuit distribution wafer (CDW) ( ) are used to wafer-level test a product wafer ( ) containing one or more product integrated circuits (ICs). The CDW ( ) contains circuitry which is used to test the ICs on the product wafers ( ). A connection from the product wafer ( ) to the CDW ( ) is made via a compliant interconnect media (IM) ( ). Through IM ( ), the CDW ( ) tests the product wafer ( ) under any set of test conditions. Through external connectors and conductors ( , and ) the CDW ( ) transmits and receives test data, control information, temperature control, and the like from an external tester ( ). To improve performance and testability, the CDW ( ) and heating/cooling ( and ) of the wafers may be segmented into two or more wafer sections for greater control and more accurate testing.

Method for testing a product integrated circuit wafer using a stimulus integrated circuit wafer

A bump-bonded multi-chip flip-chip device (100) is formed by manufacturing a mother chip (102) having a first set (207) of bumps (212) and a second set (209) of bump contacts (210). A daughter chip (104) is also formed which has conductive bumps (312). The daughter chip (104) and the mother chip (102) are placed face-to-face and contact is made between the daughter chips bumps (312) and the mother chips bump contact regions (210). After interconnection of the daughter chip (104) and the mother chip (102), the mother chip (102) is contacted to an IC package (106) using the bumps (212). The package (106) uses a plurality of metallic layers interconnected selectively by conductive vias in order to route signals between the mother chip (102), the daughter chip (104), and external terminals (112) of the package (106).

Multi-chip semiconductor device and method for making the device by

A method, apparatus, and circuit distribution wafer (CDW) (16) are used to wafer-level test a product wafer (14) containing one or more product integrated circuits (ICs). The CDW (16) contains circuitry which is used to test the ICs on the product wafers (14). A connection from the product wafer (14) to the CDW (16) is made via a compliant interconnect media (IM) (18). Through IM (18), the CDW (16) tests the product wafer (14) under any set of test conditions. Through external connectors and conductors (20, 22, 24, and 26) the CDW (16) transmits and receives test data, control information, temperature control, and the like from an external tester (104). To improve performance and testability, the CDW (16) and heating/cooling (80 and 82) of the wafers may be segmented into two or more wafer sections for greater control and more accurate testing.

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Austin, TX, United States of America

Robert Keith DeHaven