Cornell University

Robert Karmazin

Rajit Manohar

Carlos Tadeo Ortega Otero

Methods, systems, and devices are disclosed for automatically generating physical layouts of integrated circuits. A circuit is partitioned into one or more cells based on a circuit description. The method further checks availability of a layout of a cell for all the cells generated during the partition step. If a layout of a cell is not available, the method generates a layout of the cell by an automatic tool, and packages the generated layout in a form of a standard cell compatible with a standard cell placement and routing tool. Afterwards, the generated layout may be exported to the standard cell placement and routing tool. Finally, the standard cell placement and routing tool may merge individual layouts of the one or more cells of the circuit to generate a layout for the circuit.

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Ithaca, NY, United States of America

Robert Karmazin