Texas Instruments Corporation

National Semiconductor Corporation

Robert Karl Butler

Michael Henderson Perrott

Hee Wong

Yogesh Darwhekar

Vijaya G Ceekala

Shu-Ing Ju

Srikanth Manian

Jagdish Chand Goyal

Srinivas Theertham

Madusudanan Srinivasan Gopalan

Michael Schwartz

Jim Wieser

In described examples, a phase locked loop (PLL) has a first phase detector cell (PD) that has a gain polarity. The first PD cell has a phase error output and inputs coupled to a reference frequency signal and a feedback signal. A second PD cell has an opposite gain polarity. The second PD cell has a phase error output and inputs coupled to the reference frequency signal and the feedback signal. A loop filter has a feedforward path and a (lossy) integrating path coupled to an output of the filter. The feedforward path has a third PD cell that has phase error output AC-coupled to the filter output. The integrating path includes an opamp that has an inverting input coupled to the first PD cell phase error output and a non-inverting input coupled to the second PD cell phase error output.

High gain detector techniques for high bandwidth low noise phase-locked loops

A duty cycle correction circuit, and method of operating the same, to correct the duty cycle of an input clock signal having a frequency divided-down from a reference clock by an odd-valued integer. A delay stage outputs the input clock signal delayed by one half-cycle of the reference clock, and a logic circuit outputs an extended clock signal by a logical OR of the input and delayed clock signals. A latch latches the extended clock signal when enabled by the reference clock, and a flip-flop latches the extended clock signal responsive to the reference clock. A gate selects the latch output or the flip-flop output based on the state of the delayed clock signal as an intermediate signal. A multiplexer generates the output clock by selecting between the intermediate signal and the input clock signal in alternating reference clock phases.

Duty cycle correction for high-speed clock signals

The disclosure provides a frequency synthesizer. It includes a PFD that generates an up signal and a down signal in response to a reference signal and a feedback signal. A charge pump generates a control voltage in response to the up signal and the down signal. A low pass filter generates a filtered voltage in response to the control voltage. An oscillator circuit generates an output signal in response to the filtered voltage. A feedback divider is coupled between the oscillator circuit and the PFD, and divides the output signal by a first integer divider to generate the feedback signal. A sigma delta modulator (SDM) generates a second integer divider in response to the feedback signal, the reference signal, the output signal and the first integer divider. A digital filter is coupled between the SDM and the feedback divider, and filters quantization noise associated with the SDM.

Phase noise improvement techniques for wideband fractional-N synthesizers

A cable detector includes one or more peak detectors that detect when a termination impedance is missing from the output of a line driver. A peak detection signal is asserted when signals on a transmission line exceed a threshold level. A fault condition is asserted when the peak detection signal is asserted for a sufficient length of time to indicate that an actual fault is detected. The time period required for detecting a lost or missing line termination is longer than the time periods for any one of the pathological conditions to avoid a false positive detection. After the peak detection signal is de-asserted, the fault condition will be maintained until another sufficient length of time has expired without a peak detection.

Cable detector

A system, apparatus and method are arranged for monitoring an input signal for a line driver and determining if a valid data signal is present. When the input signal is determined to be an invalid data signal, an offset is introduced into the input stage of the line driver to prevent noise induced toggling of the output of the line driver. When the input signal is determined to be a valid data signal, the offset is removed from the input stage since inclusion of the offset can introduce undesirable duty cycle distortion in the output of the line driver. By dynamically adding or removing the offset from the input stage of the line driver, invalid signals are prevented from toggling the output of the line driver while preserving a clean data transmission for valid signals.

Cable driver using signal detect to control input stage offset

The present disclosure relates to a system, apparatus and method for a line driver circuit to generate a signal detect (SD) signal when an invalid data signal is detected at its input. An invalid signal may be present either when no signal is available or when the line driver circuit or another component in the system (e.g., a crosspoint switch, a multiplexer, etc.) fails. The SD signal is coupled to an external controller that can either power down the line driver circuit to save power when no signal is available, or change over to a different line driver circuit or other component of the system when a failure is identified. When the input signal is determined to be a valid data signal via the SD signal, the line driver circuit can be enabled for operation. The described systems, apparatus and methods can save the user from having to directly control the line driver power state, especially in systems with large router configurations that may include hundreds of line drivers.

Signal detector output for cable driver applications

A radio frequency (RF) demodulation circuit comprising a harmonic rejection mixing stage capable of receiving and mixing an incoming radio frequency (RF) signal having a frequency RF and a reference local oscillator (LO) signal having a frequency LO and generating an output signal in which out-of-band harmonic signals are suppressed. The harmonic rejection mixing stage comprises 1) a multiphase local oscillator (LO) generator for receiving the reference LO signal and generating M phase-shifted local oscillator signals having frequencies LO and 2) M mixers, each of the M mixers receiving the incoming radio frequency signal and one of the M phase-shifted local oscillator signals. Each of the M mixers generates a subcomponent signal. The subcomponent signals are then scaled and combined to produce the output signal.

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Issaquah, WA, United States of America

Robert Karl Butler