Ams Ag

Ams International Ag

Robert Kappel

Nenad Lilic

Georg Röhrer

Georg Roehrer

Manfred Lueger

Mario Manninger

Christian Mautner

Kerry Glover

Todd Nicholas Bishop

Friedrich Bahnmueller

Friedrich Bahnmüller

Friedrich Laengauer

Daniel Furrer

Yiming Jiang

Hesong Xu

Daniele Perenzoni

Friedrich Längauer

A time-to-digital converter circuit is disclosed, the time-to-digital converter circuit including a plurality of delay stages connected to form a delay line, a plurality of event counters, an encoder circuit for triggering the delay line, and a binning circuit for associating an event with an event counter from plurality of event counters. The binning circuit selects the event counter based on a signal from the delay line, and wherein the encoder circuit is configured to sequentially trigger a different delay stage of the plurality of delay stages. Also disclosed is a time-of-flight sensor implementing the time-to-digital converter circuit, and an associated apparatus and method.

Time-to-digital converter

An optical sensor module for time-of-flight measurement comprises an optical emitter, a main detector and a reference detector which are arranged in or on a carrier. An opaque housing of the optical sensor module has a first chamber and a second chamber which are separated by a light barrier. The housing has a cover section and is arranged on the carrier such that the optical emitter is located inside the first chamber, the main detector is located inside the second chamber and the reference detector is located outside the first chamber. Furthermore, a main surface of the cover section is positioned opposite the carrier. The optical emitter is arranged and configured to emit light through a first aperture in the cover section, and the main detector is arranged and configured to detect light entering the second chamber through a second aperture in the cover section. A reference path is established between the optical emitter and the reference detector inside the optical sensor module, and confined by the main surface of the cover section and the carrier. Additionally, a method for manufacturing an optical sensor module for time-of-flight measurement is presented.

Optical sensor module and method for manufacturing an optical sensor module for time-of-flight measurement

A semiconductor body includes a driver for driving a light source, at least two detectors each including an avalanche diode, a time-to-digital converter arrangement coupled to outputs of the at least two detectors, a memory that is coupled to the time-to-digital converter arrangement and is configured to store at least one histogram, and an evaluation unit coupled to the driver and to the memory.

Measuring time-of-flight using a plurality of detector subsystems and histogram storage

A directional photodetector comprises a photosensitive element and a light selector. The photosensitive element comprises a single-photon avalanche diode, SPAD, or an array of SPADs or SPAD array. The light selector is arranged on or above the photosensitive element, in particular on or above an active surface of the photosensitive element. The light selector is configured to restrict a field of view of the photosensitive element at least for light with a wavelength within a specified wavelength range. The light selector is configured to restrict the field of view by predominantly passing light with a direction of incidence within a range of passing directions of the light selector.

Directional photodetector and optical sensor arrangement

The SPAD device comprises a single-photon avalanche diode and a further single-photon avalanche diode having breakdown voltages, the single-photon avalanche diodes being integrated in the same device. The breakdown voltages are equal or differ by less than 10%. The single-photon avalanche diode is configured to enable to induce triggering or to have a dark count rate that is higher than the dark count rate of the further single-photon avalanche diode.

SPAD device for excess bias monitoring

A charge pump circuit arrangement includes a multitude of capacitors of a first and a second group controlled by non-overlapping clock pulses. The capacitors are partly realized in a semiconductor substrate including a deep well doping region and a high voltage doping region surrounded by the deep well doping region. Switches are connected to a pair of capacitors to control the deep well doping regions with signals in phase with the corresponding clock signal.

Charge pump circuit arrangement

The semiconductor device comprises a bipolar transistor with emitter, base and collector, a current or voltage source electrically connected with the emitter, and a quenching component electrically connected with the collector, the bipolar transistor being configured for operation at a collector-to-base voltage above the breakdown voltage.

Semiconductor device with single electron counting capability

A avalanche diode arrangement comprises an avalanche diode () that is coupled to a first voltage terminal () and to a first node (), a latch comparator () with a first input () coupled to the first node (), a second input () for receiving a reference voltage (VREF) and an enable input () for receiving a comparator enable signal (CLK), and a quenching circuit () coupled to the first node ().

Avalanche diode arrangement and method for controlling an avalanche diode arrangement

The device comprises a bipolar transistor with emitter, base, collector, base-collector junction and base-emitter junction, a collector-to-base breakdown voltage, a quenching component electrically connected with the base or the collector, and a switching circuitry configured to apply a forward bias to the base-emitter junction. The bipolar transistor is configured for operation at a reverse collector-to-base voltage above the breakdown voltage.

Light emitting semiconductor device for generation of short light pulses

A time-to-digital converter arrangement has a ring oscillator with a plurality of inverting elements and a first and a second counter coupled to the ring oscillator. The first counter is configured to increment a first counter value if a positive edge transition is present at one of the inverting elements. The second counter is configured to increment a second counter value if a negative edge transition is present at the one of the inverting elements. A storage element stores the first and the second counter value and logical states of the plurality of inverting elements. A decoder coupled to the storage element selects one of the first and the second counter value as a valid value based on an evaluation of the stored logical states, and outputs a total counter value based on the valid value and the stored logical states.

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Wettmannstaetten, Austria

Robert Kappel