Sun Microsystems, Inc.

Aditazz, Inc.

Lsi Logic Corporation

Agate Logic, Inc.

Cswitch Corporation

Robert K Yu

Grzegorz B Zyner

Satish Padmanabhan

Deepak Aatresh

Sungmin Kim

Mukunda Krishnappa

Sudha Hajela

Dave Trossen

Kevin James

John Victor-Faichney

Dana How

Malcolm J Wing

Godfrey P D'Souza

Jay B Patel

J Arjun Prabhu

Colin Neal Murphy

Pohrong Rita Chu

Douglas A Laird

Ivo J Dobbelaere

Manjunath Doreswamy

Suresh Subramaniam

Nasima Parveen

Chakra R Srivatsa

Jason Golbus

Scott Ewart

Shailesh I Shah

Sophia Lin

Jack Liu

Gregory B Zyner

Paul Yip

A computer-implemented method for generating multiple room placements is disclosed. In the embodiment, the method involves obtaining information indicating a number of rooms to be placed in a department, the information including room type information, capturing at least one room pattern using a pattern language-based regular expression, and generating a plurality of room placements using the at least one room pattern by placing the rooms to be placed in the department according to the selected room pattern.

Method and system for placing rooms in a department

Computer based methods and systems for characterizing the energy use of multiple different building massing configurations are disclosed. In one embodiment, a computer based method involves specifying a set of parameters for a building massing configuration, calculating a normalized energy use index for multiple different building massing configurations that meet the specified set of parameters, wherein the normalized energy use index for each of the multiple different building massing configurations is normalized against a reference energy use index of a reference building, ranking the multiple different building massing configurations by the respective normalized energy use indexes, and selecting at least one of the different massing configurations for display on a graphical user interface according to the ranking.

System and method for evaluating the energy use of multiple different building massing configurations

A computer-implemented method for right-sizing function-specific blocks in a healthcare building with a given architectural parti to support a specific space program is disclosed. In an embodiment, the method involves describing the relative locations of function-specific blocks using a coordinate system, wherein the function-specific blocks are placed in particular locations within the building relative to a circulation pattern, describing constraints related to the areas of the function-specific blocks, and adjusting the areas and/or aspect ratios of the function-specific blocks to find a solution that maintains the relative locations of the function-specific blocks while meeting the area constraints.

Method and system for right-sizing function-specific blocks in a healthcare building with a given architectural parti to support a specific space program

Computer based methods and systems for evaluating different building designs are disclosed. In one embodiment, the method involves generating a first set of different building massing configurations using a shape grammar, storing the generated first set of different building massing configurations in a building massing library, reducing the first set of different building massing configurations according to a parameter search to form a second set of different building massing configurations, the second set being a subset of the first set, and using the second set of different building massing configurations to evaluate an aspect of a building system.

System and method for realizing a building using automated building massing configuration generation

A system for determining memory addresses including a first content-addressable memory (CAM) configured to generate a first matchvector based on a first key; a first inverse-mask-reverse (IMR) module operatively connected to the first CAM, where the first IMR module is configured to generate a first auxiliary matchvector based on the first matchvector; and a first priority encoder (PE) operatively connected to the first IMR module, where the first PE is configured to output a first encoded memory address based on the first auxiliary matchvector, where the first CAM, the first IMR module, and the first PE are associated with a first reconfigurable content-addressable memory (RCAM).

Reconfigurable content-addressable memory

A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.

Heterogeneous configurable integrated circuit

A multiplication accumulation circuit (abbreviated as &ldquo;MAC&rdquo;) has five input buses that carry signals for operands A, B, C, D and E, a control bus that carries signals for controlling the operations performed on the received operands, and an output bus that carries a signal generated by the MAC. Each of operands A, B, C and D can be four different operands that are used as follows by the MAC: (1) to perform two multiplications simultaneously, and (2) to perform an addition of the products of the two multiplications and the fifth operand E, e.g. generate on the output bus a signal of value A*C&plus;B*D&plus;E. Alternatively, operands A and B can be, respectively, the upper and lower halves of a first double word to be used as a multiplicand. Similarly, operands C and D can be the upper and lower halves of a second double word to be used as a multiplier. In this case, the four operands A, B, C and D are used as follows by the MAC: (1) to perform a single multiplication of the first double word with the second double word, and (2) to perform an addition of the product of the double word multiplication, and the fifth operand E, e.g. generate on the output bus a signal of value &lsqb;A,B&rsqb;*&lsqb;C,D&rsqb;&plus;E.

Circuit and method for multiplying and accumulating the sum of two products in a single cycle

A Viterbi calculator performs additions in parallel with comparison to compute the result of a single Viterbi equation in a single clock cycle. Therefore, the results of a butterfly operation involving two Viterbi equations can be computed in a single clock cycle by use of two Viterbi calculators. Alternatively, the butterfly operation can be implemented by a single Viterbi calculator used in a pipelined manner, although the throughput is at the rate of every two clock cycles. When a single Viterbi calculator is used in the pipelined manner, two multiplexers are used to alternately swap the constant values being supplied to the Viterbi calculator. The pipelined use of a single Viterbi calculator requires less space on an integrated circuit die than the parallel use of two Viterbi calculators, and is useful in applications where the variable data is available every two clock cycles (e.g. due to latency in accessing memory).

Apparatus and method for computing the result of a viterbi equation in a

Quotient digit selection logic is modified so as to prevent a partial remainder equal to the negative divisor from occurring. An enhanced quotient digit selection function prevents the working partial remainder from becoming negative if the result is exact, choosing a quotient digit of zero instead of a quotient digit of one when the actual partial remainder is zero. Using a five bit estimated partial remainder where the upper four bits are zero, a possible carry propagation into fourth most significant bit is detected. This can be accomplished by looking at the fifth most significant sum and carry bits of the redundant partial remainder. If they are both zero, then a carry propagation out of that bit position into the least significant position of the estimated partial remainder is not possible, and a quotient digit of zero is chosen. This provides a one cycle savings since negative partial remainders no longer need to be restored before calculating the sticky bit. Extra hardware is eliminated because it is no longer necessary to provide any extra mechanism for restoring the preliminary final partial remainder. Latency is improved because no additional cycle time is required to restore negative preliminary partial remainders. In an alternative embodiment, where the upper four bits of the estimated partial remainder are ones while the fifth most significant bit is zero, a quotient digit of negative one is chosen. This alternative embodiment allows correct exact results in all rounding modes including rounding toward plus or minus infinity.

Quotient digit selection logic for floating point division/square root

A method of improving the timing performance of a circuit includes the step of producing a first set of timing results from a static timing analyzer operating on a netlist that characterizes a circuit. A critical timing path within the circuit is then identified from the first set of timing results. The critical timing path is then converted into an equivalent schematic circuit representation. A simulation of the equivalent schematic circuit representation on a circuit simulator produces a second set of timing results. Timing discrepancies are then located between the first set of timing results and the second set of timing results. Based upon the timing discrepancies, cells are substituted into the critical timing path to improve the timing performance of the critical timing path.

Apparatus and method for verifying the timing performance of critical

A floating point multiplier with partial support for subnormal operands and results uses radix-4 or modified Booth encoding and a binary tree of 4:2 compressors to generate the 53.times.53 double-precision product. Delay matching techniques in the binary tree stage and in the final addition stage reduce cycle time. Improved rounding and sticky-bit generating techniques further reduce area and timing. The overall multiplier has a latency of 3 cycles, a throughput of 1 cycle, and a cycle time of 6.0 ns.

Floating point multiplier with reduced critical paths using delay

A floating point mantissa final addition and rounding unit uses a conditional sum adder to reduce a redundant carry-save format 106-bit mantissa to a non-redundant properly rounded 53-bit double-precision mantissa. The conditional sum adder simultaneously speculatively computes both the sum and the incremented sum of the upper 52 bits of the carry-save portions. A rounding unit speculatively computes the lower one bit and two bits of the mantissa for the cases of mantissa overflow or non-overflow, respectively. The rounding unit produces an overflow carry signal and a non-overflow carry signal. A multiplexor selects the proper 53 mantissa output bits from among the two conditional sum adder outputs and the rounding unit mantissa outputs depending upon the most significant bits of the two conditional sum adder outputs and the overflow and non-overflow carry signals. The floating point mantissa final addition and rounding unit is used to perform the final addition and rounding for a multiplier that produces a 106-bit carry-save result and for a division/square root unit that produces a 56-bit non-redundant result. A multiplexor selects the input from among the multiplier carry-save result and the division/square root unit non-redundant result. When the division/square root result is selected, the carry portion and the less significant 50 bits of the sum portion are set equal to zero. When a non-redundant result is input into the final addition and rounding unit, the conditional sum adder acts merely as an incrementer.

Shared rounding hardware for multiplier and divider/square root unit

The same hardware is used to implement calculations of the exponents for multiplication, division, and square root in either double or single precision. A multiplexor selects the appropriate bias value necessary for exponent computation for the given instruction type, operand precision, and output precision. A first operand multiplexor selects either the exponent of the first operand in the case of a multiplication or division instruction, and selects zero in the case of a square root instruction, since the square root operation only requires one operand. The second operand multiplexor selects the second exponent in the case of a multiplication instruction, the one's complement of the second exponent in the case of a division instruction, and the second exponent divided by two during a square root operation. Flip-flop registers latch the exponent and incremented exponent when a division or square root operation is pending. A multiplexor select between the presently calculated exponents and the saved exponents calculated for a pending division or square root operation. If the instruction scheduler has flexibility in allowing out of order instruction completion, younger multiplication instructions can be dispatched and completed during the several machine cycles during which the division/square root mantissa computation.

Shared hardware for multiply, divide, and square root exponent

A method for fully supporting floating point multiplication using a combination of partial hardware support and partial software support traps to software when a subnormal operand is encountered and gross underflow cannot be determined without determining the leading zeros in the subnormal mantissa. A simplified hardware multiplier does not require leading zero detection or left or right shifting. The partial hardware support circuit allows single and double precision operands. The hardware multiplier unit only partially supports subnormal operands. If one of the operands is subnormal, the hardware multiplier unit will output zero and a gross underflow signal if the multiplication would result in gross underflow. There is a small minority of operand permutations that are not supported in hardware and thus require a greater time to compute by resorting to software. However, the vast majority of operand permutations gain reduced latency. So long as the fraction of operand permutations that occurs when a typical instruction stream is executing that are not supported in hardware is small, a performance gain is achieved. An alternative embodiment of the present invention, the gross underflow output is computed in parallel with the resulting exponent computation. An implementation of the gross underflow detection circuit can be used for either single or double precision operands.

Growing community of inventors

Newark, CA, United States of America

Robert K Yu