Texas Instruments Corporation

Other

Robert K Peterson

Burhan Ozmat

Larry J Mowatt

Aaron D Poteet

Larry K Johnson

Austin S O'Malley

Robert M Fife

Robert J Gordon

Walter L Walas

Aubrey Chapman

Brian J Love

Maurice M Guy

A method of making semiconductor package and the package comprising the steps of providing a base having a plurality of cavities therein, forming a plurality of sets of spaced apart first apertures extending entirely through the base, each of the sets of spaced apart first apertures surrounding one of the cavities, forming a plurality of sets of second apertures extending partially through the base, each of the second apertures of a set being interconnected with a pair of adjacent ones of the first apertures from one of the sets to form a continuous groove extending partially through the base and surrounding one of the cavities and then causing the second apertures to extend entirely through the base to form individual packages associated with each of the cavities. The base is a cast base and the first and second apertures are preferably said base. The second apertures are caused to extend entirely through the base to separate the packages by punching out the remaining portion of the base disposed in the second apertures. Electrical elements are disposed in the cavity and an overlay is provided over the package providing interconnects to the electrical elements in the cavity. The remainder of the cavity is preferably with a potting composition. Optionally, solder balls can be secured to the interconnects and cooling fins can be provided in the base. The base can also be a thin sheet having plurality cavities which can be sawed apart, the thickness of the sheet being at most about the same as the height dimension of the elements disposed within the cavity.

Integrated circuit packaging

First and second electronic parts interconnected by a nonconductive nanoporous film having first and second parallel surfaces, said film having metal-filled pores extending through the thickness of the film, such that each of said parts is contacted by the metal in at least several pores, a number of the pores being perpendicular to the surfaces of the film, and other pores being oblique to the surfaces of the film, whereby thermal dissipation is enhanced in the plane of the film.

Microelectronic assemblies including Z-axis conductive films

A method of making a semiconductor package and the package comprising the steps of providing a base having a plurality of cavities therein, forming a plurality of sets of spaced apart first apertures extending entirely through the base, each of the sets of spaced apart first apertures surrounding one of the cavities, forming a plurality of sets of second apertures extending partially through the base, each of the second apertures of a set being interconnected with a pair of adjacent ones of the first apertures from one of the sets to form a continuous groove extending partially through the base and surrounding one of the cavities and then causing the second apertures to extend entirely through the base to form individual packages associated with each of the cavities. The base is a cast base and the first and second apertures are preferably cast into said base. The second apertures are caused to extend entirely through the base to separate the packages by punching out the remaining portion of the base disposed in the second apertures. Electrical elements are disposed in the cavity and an overlay is provided over the package providing interconnects to the electrical elements in the cavity. The remainder of the cavity is preferably with a potting composition. Optionally, solder balls can be secured to the interconnects and cooling fins can be provided in the base. The base can also be a thin sheet having plurality cavities which can be sawed apart, the thickness of the sheet being at most about the same as the height dimension of the elements disposed within the cavity.

Integrated circuit packaging method and the package

A thermal core (10) including aluminum layer (12) held between two molybdenum layers (14) for dissipating heat from a plurality of chip carriers (22). Core (10) has the ability to withstand excessive vibrational loads while being lightweight. Bonding molybdenum/aluminum/molybdenum layers (12, 14) creates a core (10) having an increased stiffness factor which surpasses military vibrational requirements. Additionally, due to the low density of porous aluminum layer (12), weight limitations set forth by the military can also be met.

Constraining core for surface mount technology

A method of forming a z-axis interface with a device having a first electrically conductive pad thereon wherein a layer of resilient electrically insulating material, capable of being made rigid, preferably a thermoplastic polymer or a b-stage thermosetting polymer, is formed over the first pad. A via is then formed in the electrically insulating material extending to the first pad. A layer of electrically conductive material, preferably gold, is then formed on the sidewalls extending to the pad and out of the via. A second electrically conductive pad is then applied under pressure to the electrically conductive material extending out of the via to deform the electrically conductive material into the resilient electrically insulating material. The electrically insulating material is then caused to become rigid. In accordance with a second embodiment, a free standing interconnect structure is provided by providing a removable base, forming a patterned electrically conductive layer on the base, forming a layer of resilient electrically insulating material, capable of being made rigid, and having a via with sidewalls extending therethrough secured to the electrically conductive layer, forming a layer of electrically conductive material on the sidewalls extending out of the via and over the electrically insulating material and removing the removable base.

Bonded z-axis interface

A multilayer microwave structure for digital, power, RF and other interconnects wherein the metal (3, 7) and insulator (9) structure is built up in additive sequential steps over a base (5). Hermeticity within the structure is provided by forming an oxide layer (65) within the insulator portion of the structure which contacts the metal at all perimeter portions thereof.

Method of fabricating microwave interconnects and packaging and the

A capped MMIC and method of making same wherein a polymer layer cast over the surface of a semiconductor wafer and vias are formed in the polymer layer down to the wafer surface. The exposed surface of the polymer layer is then metallized and etched in a predetermined pattern to provide a metal pattern over the upper surface of the polymer layer which extends into the vias and to the surface of the wafer. Pads of the metallization are also provided on the upper surface of the polymer layer which are individually electrically isolated from the remainder of the metallization. The wafer is now ground back and backside metallization and other desired processing then takes place in standard manner to complete fabrication of the individual MMICs on the wafer. The MMICs are then diced in standard manner. The MMICs can be secured in a housing fabricated of ceramic or metal. The housing has a plurality of cavities, each cavity for receipt of a MMIC or MMICs. A ground plane is provided along the surface of the housing by plating or the like, if the housing is ceramic (the housing can be its own ground plane if electrically conductive), this ground plane being coupled to the metallization on the MMIC to provide a continuous ground plane along the top surface of the housing with pads on the surface of the MMIC electrically isolated from the ground plane. A multilayer circuit can be fabricated over the ground plane layer and can contain passive elements thereon, such as couplers, filters, transmission lines and the like which are coupled through vias therein to pads on the MMICs.

Method of making a capped modular microwave integrated circuit

Capped modular microwave integrated circuit and method of making same

A printed wiring board is comprised of a combination of layers providing a good thermal match with surface mount components. The board consists of a core surrounded by multiple layers of dielectric and conductive materials optimized for their thermal expansion qualities. The core is also used as the tooling plate during manufacture. Side-to-side interconnects are made by blind-plated vias and through-holes in the core.

Advanced polymers on metal printed wiring board

An electronic system having a first printed wiring board, a first integrated circuit carrier positionable on the printed wiring board and a substrate having a central portion formed of ceramic material. The substrate central portion has a specific thermal conductivity greater than 1.5.times.10.sup.-5 Wm.sup.2 /g.degree.C. The substrate may comprise a ceramic material formed in combination with a modifier of the type which increases fracture toughness thereby inhibiting crack initiation and growth. In an alternate form of the invention the elctronic system includes a substrate having a central portion formed of ceramic material and first and second opposing surfaces each clad with a metallic layer of predetermined thickness. The combination of the substrate and the bonded wiring boards provide an effective coefficient of thermal expansion to each wiring board which is sufficiently close to the coefficient of thermal expansion of the carriers so as to prevent solder joint cracking during operation of the system.

Ceramic based substrate for electronic circuit system modules

A printed wiring board is comprised of a combination of layers providing a good thermal match with surface mount components. The board consists of a core surrounded by multiple layers of dielectric and conductive materials optimized for their thermal expansion qualities. The core is also used as a heat sink for drawing excess heat from the components. An integral thermal interface region is used to dissipate the heat from the core.

Thermal interface for a printed wiring board

A circuit board system resiliently mounts a plurality of daughter boards with high circuit interconnection density on a mother board using pairs of mating connectors having welded contact members accommodated in novel arrangements in the respective connectors to permit high density of electrical interconnection with convenience and reliability. Contact parts of substantial size are welded into contacts in one connector to detachably interconnect with contact parts of similar size in mating connector to improve interconnection releability. Novel contact arrangements permit accommodation of those parts of substantial size in the mating connectors. Sheet metal spring or post parts welded into the contacts in both connectors permit the contacts to be conveniently loaded into connector bodies and permit large numbers of contact springs or posts to be soldered to terminal pads or circuit paths on mother or daughter boards with high density. Temporary fixtures mount on connectors to facilitate precise soldering of leaf springs to very closely spaced terminal pads on daughter boards; resilient mounting of the mother board facilitate daughter board engagement with heat sinks; and organizer plates fit on extending ends of connector contact posts to facilitate their insertion into mother board mounting holes with high interconnection density.

Circuit board systems, connectors used therein, and methods for making

A semiconductor chip carrier system has a printed circuit board supporting a plurality of ceramic carrier packages in rows and columns; each package has a plurality of flexible electrical conductive connection pads. A plurality of pressure exerting retaining means engage columns of the ceramic packages. The ends of the retaining means are connected to the printed circuit board for retaining the flexible electrical conductive connection pads of the columns of ceramic carrier packages in electrical contact with the printed circuit board thereby eliminating the need for solder connections.

High pin count chip carrier package

An improved planar (flat plate) array antenna system and method of fabrication is disclosed. A planar array antenna or array is mounted in a support for stabilization against roll and pitch movements with a rotary joint providing uninterrupted radar operation. The array is scanned in azimuth up to 120 rpm with elevation or tilt control. The support arrangement is a four gimbal arrangement providing for a high r-f gain to swept volume ratio for a forward looking radar with fast azimuth scan. The array comprises a front plate and a back plate attached to spaced flanged beams and end shorts for forming a plurality of RF energy cavities. The front plate has radiation output ports (shunt slots) covered with a Kapton layer for closing the array cavities against moisture and to permit pressurization to prevent arcing. The back plate has power divider slots (series slots) over which a manifold is disposed for distributing RF energy into the array. The flanges of the flanged beams provide the increased bonding area necessary to retain the front and back plates during cavity pressurization.

Growing community of inventors

Garland, TX, United States of America

Robert K Peterson