International Business Machines Corporation

Robert K Montoye

Leland Chang

Jae-sun Seo

Jeffrey Haskell Derby

Dharmendra S Modha

Chung H Lam

Daniel Joseph Friedman

Jose A Tierno

Bernard V Brezzo

Hung Cai Ngo

Yutaka Nakamura

Michael K Gschwind

Bipin Rajendran

Jing Li

Brian L Ji

Wendy Ann Belluomini

John-David Wellman

Philip George Emma

Brett Olsson

Dheeraj Sreedhar

Robert H Dennard

John Vernon Arthur

Kevin John Nowka

Paul A Merolla

Steven Kyle Esser

Gary S Ditlow

Yong Liu

Chandler Todd McDowell

Ramyanshu Datta

David William Boerstler

Jente Benedict Kuang

William Robert Reohr

Wing Kin Luk

Daniel Jonathan Auerbach

Harm Peter Hofstee

Michele M Franceschini

Saravanan Sethuraman

Lawrence Shungwei Mok

Vijayalakshmi Srinivasan

Diyanesh B Chinnakkonda Vidyapoornachary

Kailash Gopalakrishnan

Edgar Rolando Cordero

Arthur R Zingher

Raymond R Horton

Albert M Young

David Michael Daly

Timothy Michael Kemp

Alphonso Philip Lanzetta

Andrew Kenneth Martin

Peter William Cook

John Jeremy Rice

John Davis Palmer

Stephen Larry Runyon

Peter George Capek

David Leslie Cohn

Steven Paul VanderWiel

Joseph Maryan Milewski

Mark Jay Charney

Raquel Norel

Myhong Nguyenphu

Dennis Jay McBride

John Ulrich Knickerbocker

Alper Buyuktosunoglu

Luis Alfonso Lastras-Montano

Pradip Bose

Paul Stephen Andry

Kanak Behari Agarwal

Edmund Juris Sprogis

Bartholomew Blaner

Matthew Joseph Breitwisch

Todd Edward Takken

Bruce Martin Fleischer

Anthony Correale, Jr

Jun Sawada

Sumedh Wasudeo Sathaye

Jude A Rivers

Xin Zhang

Michael Sperling

Takeo Yasuda

Victor V Zyuban

Thomas R Puzak

Charles D Johnson

Chirag Suryakant Patel

Erik Richter Altman

Charles Luther Johnson

Erdem Hokenek

Salvatore Nicholas Storino

David John Craft

Gerald Warren Gibson, Jr

John Cocke

Winfried W Wilcke

George A Katopis

Albert Y Chang

Edward Scott Kirkpatrick

Richard Francis Freitas

Jayakumaran Sivagnaname

Prashant Jayaprakash Nair

Martin Cochet

Augusto J Vega

Juan Antonio Carballo

Systems and methods for optimizing a pipeline are described. A system can generate at least one pair of single flux quantum (SFQ) clock signals based on a stream of SFQ pulses. Each pair of SFQ clock signals can include a first SFQ clock signal and a second SFQ clock signal that is out of phase with the first SFQ clock signal. The second SFQ clock signal can have the same frequency as the first SFQ clock signal. The system can define, for each pair of SFQ clock signals, a first clock cycle and a second clock cycle based on the first SFQ clock signal and the second SFQ clock signal. The second clock cycle can be greater than the first clock cycle. The system can assign the first and second clock cycles to different stages of a pipeline based on delays by the different stages.

Asymmetrical clock separation and stage delay optimization in single flux quantum logic

A system and method for supporting an interconnection of processor cores, each core with functional state monitors for monitoring operations of each processor core, the processor cores interconnected using a resistive network connected between two-terminal regions being embedded in the resistive network such that each terminal of a region may be connected by controllable resistors to one or both fixed rails or by controllable resistors to one or more intermediate nodes. The resistor values are configurable to provide indirect control of the voltages across each two-terminal region, allowing full dynamic control of voltages of the two-terminal regions in a range up to the full voltage between the two voltage rails, and where a management unit accesses the functional state monitors and controls the resistor values. Feedback from functional state monitors allow the operating frequency to extend down to arbitrarily low values and up to the limits imposed by the technology.

Stacked, reconfigurable co-regulation of processing units for ultra-wide DVFS

Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network

Single error correction ('SEC') code and triple error detection ('TED') code are used to optimize bandwidth and resilience under multiple bit failures. One or more errors in data stored in duplicated registers are detected and corrected using the SEC code and TED code where simultaneous read operations are produced with two copies of data for each of the duplicated registers for a multi-port banked memory array. The SEC code and TED code may be included in each of the two data copies of the simultaneous read operations.

Employing single error correction and triple error detection to optimize bandwidth and resilience under multiple bit failures

Systems and methods are provided for executing an instruction. The method may include loading a first vector into a first location, the first vector including a plurality of first data elements and loading a second vector into a second location, the second vector including a plurality of second data elements. The method may further include comparing the plurality of first data elements of the first vector to the plurality of data elements of the second vector and performing one or more operations on the plurality of first and second data elements based on at least one vector cross-compare instruction. The one or more operations include counting a number of data elements of the plurality of first and second data elements that satisfy at least one condition, counting a number of times specified values occur in the plurality of first and second data elements, and generating sequence counts for duplicated values.

Vector cross-compare count and sequence instructions

A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

Reconfigurable and customizable general-purpose circuits for neural networks

A central processing unit system includes: a pipeline configured to receive an instruction; and a register file partitioned into one or more subarrays where (i) the register file includes one or more computation elements and (ii) the one or more computation elements are directly connected to one or more subarrays.

Local computation logic embedded in a register file to accelerate programs

Methods, systems and computer program products for accelerating sorting of data are provided herein. A computer-implemented method includes retrieving a plurality of cache lines of data from an input buffer, wherein each cache line comprises a plurality of elements, scattering the plurality of elements of each retrieved cache line into a plurality of bins, wherein said scattering comprises using one or more vector instructions, forming a bin cache line in a corresponding one of the plurality of bins, wherein the bin cache line comprises a group of the plurality of elements which were scattered to the corresponding one of the plurality of bins, writing the bin cache line from the corresponding one of the plurality of bins to a memory, and loading the bin cache line from the memory to the input buffer.

In-memory/register vector radix sort

Methods and arrangements for joining data sets. There are accepted: a first data set which forms a table in a relational database, and a second data set which forms a table in a relational database, each of the first and second data sets comprising a key value. Each of the first and second data sets is hashed based on the key value, and are thereupon sorted based on the key value. The sorted first and second data sets are joined with one another based on the key value. Other variants and embodiments are broadly contemplated herein.

Sort-merge-join on a large architected register file

An apparatus for providing on-chip voltage-regulated power includes a switched capacitor voltage conversion circuit that receives an elevated power demand signal and operates at a base rate when the elevated power demand signal is not active and at an elevated rate when the elevated power demand signal is active. The switched capacitor voltage conversion circuit comprises an auxiliary set of transistors that are disabled, when the elevated power demand signal is not active and enabled, when the elevated power demand signal is active. The apparatus may also include a droop detection circuit that monitors a monitored power signal and activates the elevated power demand signal in response to the monitored power signal dropping below a selected voltage level. The monitored power signal may be a voltage input provided by an input power supply for the switched capacitor voltage conversion circuit. A corresponding method is also disclosed herein.

Efficient voltage conversion

An apparatus for storing data includes a latch circuit comprising a first set of transistors that propagate an input signal to an output signal and a second set of transistors that do not propagate the input signal of the latch circuit to the output signal wherein a gate pitch for the first set of transistors is substantially greater than a gate pitch for the second set of transistors. Also disclosed herein, a method for improving circuit performance includes receiving an electronic representation of a plurality of latching circuits associated with a design file and increasing transistor gate pitch for selected transistors of the plurality of latching circuits, wherein the selected transistors comprise transistors that propagate an input signal to an output signal. The method may also include fabricating a chip comprising the plurality of latching circuits. A computer program product corresponding to the method is also disclosed within.

High-speed latch circuits by selective use of large gate pitch

In one embodiment, a computer-implemented method includes issuing, to a DRAM with EIP, a first group of two or more load requests to load data from a hash table constructed from hashed join-key values of a dimension table for a hash-join procedure. A second group of two or more load requests is issued. First response data is received, responsive to the first group of load requests. The first response data is processed while awaiting second response data responsive to the second group. Processing the first response data includes identifying matches between the join-key values corresponding to entries in the load requests of the first group and one or more hash buckets in the first response data. The size of the second group of load requests is selected such that a time for processing the first response data is approximately equal to the latency in receiving the second response data.

High-performance hash joins using memory with extensive internal parallelism

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Rochester, MN, United States of America

Robert K Montoye