Synopsys, Inc.

Synopsis Incorporated

Robert K Mardjuki

Andrew J Read

Mark S Papamarcos

William F Kappauf

Peter R Jaeger

Lawrence C Widdoes, Jr

Robert K Couch

Wayne P Heideman

Norman Francis Kelly

Louis K Scheffer

Sani El-Fishawy

Melvin Rudin

L Curtis Widdoes

Michael Lee

An improved system or and method of connecting a hardware modeling element to the pin electronics circuitry of a hardware modeling system, with the improved system having circuitry and structures that will allow it to be connected to a hardware modeling system that is powered, circuitry to indicate to the pin electronics circuitry that the improved system is connected to it, circuitry to identify the hardware modeling element supported by the improved system to the hardware modeling system, circuitry to indicate to the hardware modeling system when the hardware modeling element is initialized so evaluation of it by the hardware modeling system can commence, circuitry to generate selectable supply voltages for the powering the hardware modeling element, and a hardware modeling element connector that will allow the connection of a family of hardware modeling elements to the same connector without the need to change the connector.

System for and method of connecting a hardware modeling element to a

The present invention describes a novel method and apparatus for sampling an input/output pin of an electronic device at high speeds, comprising the steps of: driving the device input/output pin through a series resistor with a middle voltage between the high and low voltages of the device; sampling and latching the voltage at the input/output pin; comparing the latched voltage at the device input/output pin with a high threshold voltage which is between the high voltage of the device and the middle voltage; comparing the latched voltage at the device input/output pin with a low threshold voltage which is between the low voltage of the device and the middle voltage; and using the results of the two comparisons to determine whether the device input/output pin is driving high, driving low, or in an input mode.

High speed three-state sampling

A hardware interface generates and synchronizes precisely timed digital signals. The hardware interface receives data bits and associated timing information for application to a Hardware Modeling Element (HME). Preferably there are at least two modules, each including a clock generating circuit which has an input for receiving a master clock signal, a divider circuit for generating therefrom a plurality of evenly timed internal clock signals, wherein a first one of the internal clock signals rises at the same time as the master clock signal, and a phase adjusting circuit for receiving a feedback control signal for adjusting a phase delay in accordance with a sensed throughput delay. Each module also includes a timing multiplexer which receives the internal clock signals and each having a plurality of data channels, each having approximately the same throughput delay. Each data channel also has an input for receiving a data bit, a controller for receiving the timing information which allows selection of the one internal clock signal which most closely matches the timing information, and an output port coupled to the HME. The timing multiplexer also has a dummy channel from which the sensed delay is determined. The sensed delay approximates the throughput delay. The dummy channel receives the first one of the internal clock signals and provides the feedback control signal. Finally, the hardware interface apparatus includes a timing adjustment control circuit for selectively delaying the output signal in one timing multiplexer to compensate for a slower throughput delay in another multiplexer.

Method and apparatus for generating and synchronizing a plurality of

An improved hardware modeling system that is preferably embodied as a stand-alone system for networked connection to one or a variety of host computers that are used to design digital electronics systems, the hardware modeling system having a network interface for communicating between the hardware modeling system and the host computer, a central processing unit for controlling operation of the hardware modeling system, a central timing unit for generating timing signals for use in the operation of the hardware modeling system including the generation of precision clocks, data formatting strobes and sample strobes, an internal pattern bus for transmission of read/write requests from the central processing unit in one operational mode and pattern sequences for stimulation of the hardware modeling element in a second operational mode, a pattern controller for controlling presentation and delivery of the pattern sequences to the pattern bus, a pattern memory connected to the pattern controller for storing stimulus pattern sequences, pin electronics circuitry which is used for driving the pattern sequences on the pattern bus to the hardware modeling element and then sensing the five state values of the hardware modeling element pins, and an adapter that is used for fixturing the hardware modeling element to the pin electronics circuitry with the adapter supporting live insertion into a powered hardware modeling system.

Hardware modeling system and method of use

An improved system for and method of connecting a hardware modeling element to the pin electronics circuitry of a hardware modeling system, with the improved system having circuitry and structures that will allow it to be connected to a hardware modeling system that is powered, circuitry to indicate to the pin electronics circuitry that the improved system is connected to it, circuitry to identify the hardware modeling element supported by the improved system to the hardware modeling system, circuitry to indicate to the hardware modeling system when the hardware modeling element is initialized so evaluation of it by the hardware modeling system can commence, circuitry to generate selectable supply voltages for the powering the hardware modeling element, and a hardware modeling element connector that will allow the connection of a family of hardware modeling elements to the same connector without the need to change the connector.

Growing community of inventors

Peasanton, CA, United States of America

Robert K Mardjuki