Micron Technology Incorporated

National Technology & Engineering Solutions of Sandia, LLC

Other

Intel Corporation

Sandia Corporation

Varioscale, Inc.

Robert K Grubbs

Farrell Martin Good

Yongjun Jeff Hu

Michael David Henry

David Ross Economy

Pengyuan Zheng

David P Adams

Kent H Zhuang

Randy J Shul

Gurpreet S Lugani

Karl Douglas Greth

Jonathan Joseph Coleman

Ronald S Goeke

Jeffrey Stevens

V Carter Hodges

Adam M Rowen

Kira L Fishgrab

John A Rogers

Bhumika Chhabra

Adam William Saxler

Andrea Gotti

Kevin Lee Baker

Santanu Sarkar

Gregory Robert Bogart

Ervin T Hill

Jay Steven Brown

Robert V Reeves

Scott Silverman

Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.

Memory device with low density thermal barrier

Techniques are described to form a liner to protect a material, such as a storage element material, from damage during subsequent operations or phases of a manufacturing process. The liner may be bonded to the material (e.g., a chalcogenide material) using a strong bond or a weak bond. In some cases, a sealant material may be deposited during an etching phase of the manufacturing process to prevent subsequent etching operations from damaging a material that has just been etched.

Protective sealant for chalcogenide material and methods for forming the same

A method of forming a microelectronic device comprises treating a base structure with a first precursor to adsorb the first precursor to a surface of the base structure and form a first material. The first precursor comprises a hydrazine-based compound including Si&#x2014;N&#x2014;Si bonds. The first material is treated with a second precursor to covert the first material into a second material. The second precursor comprises a Si-centered radical. The second material is treaded with a third precursor to covert the second material into a third material comprising Si and N. The third precursor comprises an N-centered radical. An ALD system and a method of forming a seal material through ALD are also described.

Methods of forming a microelectronic device, and related systems and additional methods

An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

Electronic devices comprising metal oxide materials and related methods and systems

An oxidation barrier for non-volatile memory with materials sensitive to temperature and/or cross contamination (e.g., chalcogenide materials) are described The barrier can be formed, for example, around the boundaries of a non-volatile memory tile (also known as a block or sub-array). For example, a non-volatile memory device can include an oxidation barrier on a side wall of a trench between adjacent memory tiles.

Dielectric barrier at non-volatile memory tile edge

A method for electroplating a nonmetallic grating including providing a nonmetallic grating; performing an atomic layer deposition (ALD) reaction to form a seed layer on the nonmetallic grating; and electroplating a metallic layer on the seed layer such that the metallic layer uniformly and conformally coats the nonmetallic grating. An apparatus including a silicon substrate having gratings with an aspect-ratio of at least 20:1; a atomic layer deposition (ALD) seed layer formed on the gratings; and an electroplated metallic layer formed on the seed layer, wherein the electroplated metallic layer uniformly and conformally coats the gratings.

Electroplated Au for conformal coating of high aspect ratio silicon structures

The present invention relates to a lateral via to provide an electrical connection to a buried conductor. In one instance, the buried conductor is a through via that extends along a first dimension, and the lateral via extends along a second dimension that is generally orthogonal to the first dimension. In another instance, the second dimension is oblique to the first dimension. Components having such lateral vias, as well as methods for creating such lateral vias are described herein.

Lateral vias for connections to buried microconductors and methods thereof

Electroplated AU for conformal coating of high aspect ratio silicon structures

Lateral vias for connections to buried microconductors

The present invention relates to the design and manufacture of an ignitable solid, where the solid is composed of an array of ignitable regions. In some examples, the array provides a three-dimensional periodic arrangement of such ignitable regions. The ignitable region can have any useful geometry and geometric arrangement within the solid, and methods of making such regions are also described herein.

Ignitable solids having an arrayed structure and methods thereof

A universal hanger device mounts components of a heating, ventilation, and air conditioning ('HVAC') system within an architectural structure. The universal hanger device allows HVAC components such as duct members to be mounted in any position and/or configuration.

Universal hanger device

Methods are described for making nanostructures that are mechanically, chemically and thermally stable at desired elevated temperatures, from nanostructure templates having a stability temperature that is less than the desired elevated temperature. The methods comprise depositing by atomic layer deposition (ALD) structural layers that are stable at the desired elevated temperatures, onto a template employing a graded temperature deposition scheme. At least one structural layer is deposited at an initial temperature that is less than or equal to the stability temperature of the template, and subsequent depositions made at incrementally increased deposition temperatures until the desired elevated temperature stability is achieved. Nanostructure templates include three dimensional (3D) polymeric templates having features on the order of 100 nm fabricated by proximity field nanopatterning (PnP) methods.

Nanostructure templating using low temperature atomic layer deposition

Growing community of inventors

Boise, ID, United States of America

Robert K Grubbs