Sgs-thomson Microelectronics Limited

Inmos Limited

Other

Robert John Simpson

Marcello Coppola

Neil Richards

Pascal Moniot

David Mouen Makoua

Pierre Dumas

Peter Thompson

Thierry Grenot

Keith Buckingham

Brian Jeremy Parsons

Vincent Cottignies

An ATM routing switch has a buffer circuit for holding cells located on queues at output ports, the buffer having a first reserve buffer capacity for cells of a first type requiring integrity of cell transmission and a first designation for use in determining a permitted path through the network, a second reserve buffer capacity for cells of the first type having a second designation for use in determining a different permitted path in the network and a third reserve buffer capacity for cells of a second type accepting some loss of cells in transmission, flow control circuitry operating to limit input of cells of either the first or second type if predetermined thresholds for the first, second or third buffer capacities are reached.

ATM switch for routing different cell types

An ATM routing switch has a plurality of output ports for handling digital signal cells on a first type requiring integrity of cell transmission and a second type accepting some loss of cells in transmission, the output ports having control circuitry to provide a plurality of queues of cells at each output port, each queue comprising only cells of a single type while each port outputs a mixture of cells of both types on a common output path flow control indicators on incoming cells being used to inhibit output of cells along any path to a destination for which a flow control indicator has indicated congestion.

Congestion avoidance in an ATM switch

An ATM routing switch for bidirectional transmission of at least two types of cell, one type accepting variable bit rate of transmission and a second type accepting some loss of cells in transmission, includes first reserve buffer capacity for cells of the first type, a second reserve buffer capacity for cells of said second type and control circuitry for generating a flow control signal (FCT) if a predetermined threshold for the first buffer capacity is reached by input of cells of said first type, and discarding input cells of said second type if a predetermined threshold for said second buffer capacity has been reached by input of cells of said second type.

ATM switch

An ATM routing switch has a plurality of input and output ports and a buffer for holding a plurality of ATM cells, the cells being held in the buffer as a plurality of queues (F0-F7), each formed as a chained list of addresses with front and back pointers identifying ends of each queue.

Cell queue formation in an ATM switch

A network of ATM routing switches transmits digital signal cells of a first type requiring integrity of transmission and a second type accepting some loss in transmission, each switch has buffer circuitry. a plurality of output ports each having a plurality of queues of cells awaiting output, each output port having control circuitry to provide in an output frame control bits indicating the type of cell, a path identifier and the existence of flow congestion at the routing switch which it outputting the frame, thereby inhibiting transmission of further frames to that location until a frame is received from that location indicating that the congestion is cleared.

ATM switch flow control

An ATM routing switch for bidirectional transmission of digital signal cells some requiring integrity of transmission while others accept some loss of cells in transmission, has a plurality of output ports each handling a plurality of cell queues and control circuitry for decoding control bits in each input cell to determine which output port is to be used, which queue is required and whether flow congestions exists at the source of the input cell.

There is disclosed control circuitry for, and a method of controlling, multiple priority level interrupt request to a microprocessor in which output circuitry for outputting an interrupt identifier is operable only in response to an interrupt signal having a higher priority status than any currently executing interrupt process, and a microprocessor system and method of controlling a microprocessor system, incorporating such circuitry.

Microprocessor system for handling multiple priority levels interrupt

An output driver circuit comprises a plurality of parallel pull up and pull down circuits each comprising at least one transistor switch switchable between on and off states and circuitry operable to maintain a desired resistance in the circuit when the transistor switch is switched on, and switch actuating circuitry including time delay circuitry for effecting a sequence of transistor switching operations in said pull-up and pull-down circuits with a time delay between successive operations, each operation effecting simultaneous switching of a transistor in one pull-up circuit and one pull-down circuit, whereby the output impedance is stabilised during a change in signal on the output terminal.

Controlled impedance transistor switch circuit

A succession of instructions are distributed between a plurality of multistage execution paths in a computer system. Each instruction is given a tag to identify the position of the instruction in the sequence and the execution paths of both that instruction and the preceding instruction. On entering an instruction in one execution path, register values are transferred from registers in a path executing a preceding instruction prior to completion of execution of that preceding instruction.

Parallel instruction execution with operand availability check during

There is described clock generation circuitry comprising: a plurality of sequentially connected delay devices, a first one of which is coupled to receive the first clock signal, each delay device being operable to produce a trigger signal and an output signal at a predetermined time after receiving a trigger signal from the previously connected delay device; control circuitry common to said delay devices for controlling said predetermined time interval; and output circuitry coupled to receive the output signals of the delay devices to produce therefrom said second clock signal.

Clock generation

In an integrated circuit, a multiplexor receives incoming data at a first rate and is controllable by a high rate clock signal to output that data serially at a second, higher rate. A processing device receives the data from the multiplexor at the higher rate and is controllable by a high rate clock signal to process that data. Clock generation circuitry receives a first clock signal at the first rate and produces the high rate signal for the processing device and the multiplexor. Clock generation circuitry includes sequentially connected delay devices, one connected to receive the first clock signal. Each delay device produces a trigger signal and an output signal a predetermined time after receiving the trigger signal from the previous delay device. A control circuit is common to the delay devices for controlling the predetermined time interval. An output circuit receives the output signals of the delay devices and produces the high rate clock signal.

A communication interface for interconnecting a computer with at least one other device has a link output circuit and a link input circuit. A link output on one device is connected to a link input on another device by a data line and a parallel strobe line. Data is transmitted on the data line in serial bit strings forming a succession of tokens of predetermined lengths. Signal transitions are provided on the parallel strobe line where no signal transition occurs on the data line. Each token includes a bit indicating the length of the token and a parity bit providing a check on bits in a preceding token.

Communication interface

An integrated circuit including a multiplexor connected to receive incoming data at a first rate and controllable by a high rate clock signal to output that data serially at a second, higher rate; a processing device coupled to receive data output from the multiplexor at the higher rate and controllable by a high rate clock signal to process that data; and clock generation circuitry connected to receive a first clock signal at said first rate and operable to produce therefrom said high rate clock signal to be supplied to the processing device and to the multiplexor. There is also described clock generation circuitry including a plurality of sequentially connected delay devices, a first one of which is coupled to receive the first clock signal, each delay device being operable to produce a trigger signal and an output signal at a predetermined time after receiving a trigger signal from the previously connected delay device; control circuits common to the delay devices for controlling the predetermined time interval; and output circuits coupled to receive the output signals of the delay devices to produce therefrom the second clock signal.

A condenser leak searching plug having a tapered body, a recess extending into the body from the larger end face thereof, a resiliently yieldable, non-protruding planar membrane covering and sealing the open side of the recess where the membrane forms the central part of a cap of elastic material which fits over the larger end of the body and a through duct extending from the recess to the smaller end face of the body.

Growing community of inventors

Bristol, United Kingdom

Robert John Simpson