Analog Devices,inc.

Robert John Brewer

Colin Gerard Lyden

Michael C W Coln

Michael C Coln

Alain Valentin Guery

Michael CW Coln

A method of estimating a change of a variable over a measurement window, including the steps of taking multiple samples of the variable during the measurement window, defining a weight to be associated with each sample, the weight varying as a function of position of the sample within the measurement window, processing the samples taking account of their weight to form an estimate of the change in the variable.

Method for determining the change of a signal, and an apparatus including a circuit arranged to implement the method

An accurate, low noise conditionally resetting integrator circuit in an analog to digital system samples, with an analog to digital converter, the output of an integrating circuit a number of times during a measuring period; isolates the input for the integrating circuit during sample event; generates a reset signal in response to the integrating circuit output reaching a predetermined level; and resets the feedback capacitor of the integrating circuit by isolating it from the amplifier circuit of the integrating circuit and connecting it to a reference source during a sample event.

Accurate low noise analog to digital converter system

An acquisition and averaging circuit is provided in which, during a sampling phase capacitors in sample blocksandare sequentially connected to the input signal to sample it and are then isolated so as to hold the sample. The capacitors are then connected to a combining/averaging arrangement such that an average of the sample values is formed.

Sample and hold apparatus

A multi-stage integrator achieves a relatively high small-signal gain, broad bandwidth, and very clean transient pulse response. Only simple amplifying stages (typically including an inverting amplifier(s)) are used. A high gain amplifier is coupled between an integrator input node and amplifier output node. A broadband single stage amplifier (which may comprise or act as a transconductor), may act as a current source for the output transistor and load, coupled between the integrator input node and output node. Preferably, a capacitance is coupled from the integrator input to the amplifier output. A frequency-selective element or network steers signal components to the single stage amplifier or the integrator appropriately to produce a combined output that has the desired characteristics.

Integrator with high gain and fast transient response

A multi-stage integrator achieves a relatively high small-signal gain, broad bandwidth, and very clean transient pulse response. Only simple inverters are used, making the design scalable to deep sub-micron with low supply voltages, a rail-to-rail output swing, and a relatively low output impedance and useful tolerance to capacitive loading. A high gain amplifier is coupled between an integrator input node and amplifier output node. A broadband transconductor is coupled between the integrator input node and integrator output node. A resistor connects the amplifier output node and the integrator output, while a capacitor is coupled from the integrator input to the amplifier output. The conductance of the resistor (the reciprocal of the resistance, or 1/R) is selected to be substantially equal to the transconductance g of the transconductor. A method for achieving clean transient pulse response is also described.

Operational amplifier

An improved chopped CMOS operational amplifier that includes a modulator having differential input and output connections, an AC amplifier coupled to the modulator output, a demodulator coupled to the AC amplifier output, and an integrator coupled to the demodulator output. The improvement is realized in that the operational amplifier has a gain path comprising at least four inverting amplifiers, wherein three or a greater odd number of the inverting amplifiers comprise an integrator that is rendered stable by incorporating a nested integrating capacitor within the integrator, and at least one of the inverting amplifiers is coupled to the modulator output and configured as the AC amplifier. In another aspect of the invention, a second demodulator is introduced to derive a compensating signal that tends to counteract offset voltage components attributable to modulator switch mismatch. In a further aspect of the invention, an interface network is inserted between the modulator and the AC amplifier to open the main signal path during transitions of the modulator clock signals.

CMOS operational amplifier

A digital filter includes a pre-filter cascaded to a low pass filter. The pre-filter has a transfer function providing generally increasing attenuation with increasing frequency above a cutoff frequency. The low pass filter has a transfer function providing substantially decreasing attenuation with increasing frequency above the cutoff frequency. The low pass filter is an FIR filter including coefficients restricted to the set {+1, 0 and -1}. The filters are preferably implemented using simple hardware such as addressable read/write RAM, digital adder/subtracters, and registers. Alternatively, the addressable RAM can be replaced with shift registers. Such a filter is easily and economically implemented and has a favorable overall frequency response characteristic. The filter is, therefore, well suited for use in many digital applications and, in particular, for use as a decimation filter in an oversampled, multi-bit, high order analog-to-digital converter system.

Two-stage decimation filter

A charge pump circuit for providing a bipolar voltage output at substantially double the unipolar voltage input source includes first and second voltage input terminals; a first and a second capacitor; a first switching device for selectively connecting first and second capacitors across the input terminals to charge each to the voltage of the input source; first and second voltage output terminals; a second switching device for selectively connecting the capacitors in series between one of the input terminals and one of the output terminals to generate a first polarity voltage which is substantially double the voltage of the input source; a third switching device for selectively connecting at least one of the capacitors in series between the other of the input terminals and the other of the output terminals to generate a second polarity voltage which is substantially double the voltage of the input source; and a clock for sequentially, selectively actuating the first, second and third switching devices.

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Lambourn, United Kingdom

Robert John Brewer