Omnivision Technologies, Inc.

Aptina Imaging Corporation

Micron Technology Incorporated

Aker Solutions As

Aker Subsea As

Robert Johansson

Tore Martinussen

Johannes Solhusvik

Trygve Willassen

Steffen Skaug

Olivier Bulteel

Trung Thanh Nguyen

Stuart Spitz

Timothy Bales

A wellhead system includes a wellhead assembly which is generally tubular, a landing string assembly, and an orientation sensor assembly which is mounted on the landing string assembly. The wellhead assembly is secured to a top of a borehole and has an orientation engagement part. The landing string assembly is lowered into the wellhead assembly to land in the wellhead assembly. The landing string assembly has an orientation part with an orientation feature. The orientation engagement part of the wellhead assembly corresponds to the orientation feature. As the landing string assembly is lowered into the wellhead assembly, the orientation feature engages with the orientation engagement part to rotate the landing string assembly about its longitudinal axis into a desired orientation relative to the wellhead assembly. The orientation sensor assembly measures an angular rotation of the landing string assembly about its longitudinal axis.

Wellhead system

A low power SRAM (static RAM) for an image sensor includes a voltage generation circuit for providing a positive supply voltage Vand a negative supply V, wherein VDD&#x3e;V&#x3e;V&#x3e;V; a plurality of memory cells coupled to a respective plurality of column sense lines in a pixel array, the plurality of memory cells receiving differential inputs dp and dn; and a Gray counter coupled to switchably couple Vand Vto the differential inputs dp and dn of the plurality of memory cells. A method of operating an image sensor with a low power SRAM includes acquiring an image by the image sensor; generating Vand Vsuch that V&#x3e;V&#x3e;V&#x3e;V; receiving an output g of a column of pixels at a clock input of a memory cell; and switchably coupling Vand Vto the differential inputs dp and dn of a plurality of memory cells in the SRAM according to a codeword from a Gray counter.

Low power static random-access memory

A threshold detection circuit includes a plurality of capacitors. A plurality of switching circuits is coupled to the capacitors such that a first end of each of the capacitors is coupled to a corresponding photon sensor during detection intervals, and the first end of each capacitor is coupled to a variable initialization value during reset intervals. A threshold number of the capacitors are initialized to a first value and the remaining capacitors are initialized to a second value during reset intervals. A comparator is coupled to a second of the capacitors to generate a detection event in response to the threshold number of photon sensors sensing one or more incident photons during detection intervals.

Photon sensing with threshold detection using capacitor-based comparator

An example apparatus for random sampling for horizontal noise reduction includes readout circuitry coupled to receive image data from an array of pixels, the readout circuitry including a plurality of sample and hold (S&H) circuits coupled to respective ones of a plurality of bitlines to sample and hold the image data in response to a plurality of S&H control signals, each of the plurality of S&H circuits including an S&H capacitor and an S&H switch. The S&H capacitor samples and holds respective image data, and the S&H switch coupled between a respective bitline and the respective S&H capacitor, and further coupled to receive a respective one of the plurality of S&H control signals to open/close the S&H switch, where each of the plurality of S&H switches are opened to decouple their respective S&H capacitors from the respective bitlines at a different time.

Random sampling for horizontal noise reduction

A novel image sensor includes error detection circuitry for detecting sequencing errors. In a particular embodiment a pattern is inserted into a captured image and an image processor detects sequencing errors by determining a location of the pattern. In a more particular embodiment, the image sensor includes a pixel array, arranged in columns and rows. A row select signal is encoded as a bitwise signal, and the bitwise signal is decoded by a multi-input AND gate associated with a particular column of the image sensor, based on a relationship between rows and columns of the pixel array. The relationship determines the pattern asserted into the captured image.

Image sensor failure detection

A method of implementing Correlated Multi-Sampling (CMS) in an image sensor with improved analog-to-digital converter (ADC) linearity starts with an ADC circuitry included in a readout circuitry that generates a plurality of uncorrelated random numbers used as a plurality of ADC pedestals for sampling image data. A Successive Approximation Register (SAR) included in the ADC circuitry stores a different one of the ADC pedestals before each sampling of the image data. The ADC circuitry samples an image data from a row a plurality of times against plurality of ADC pedestals to obtain a plurality of sampled input data. The ADC circuitry converts each of the plurality of sampled input data from analog to digital, which includes performing a binary search using the SAR. Other embodiments are also described.

Method and system for implementing correlated multi-sampling with improved analog-to-digital converter linearity

A method of reading out a pixel includes resetting a photodetector of the pixel. Light incident on the photodetector is then integrated for a single exposure of a single image capture. A floating diffusion node of the pixel is then reset. The floating diffusion is set to low conversion gain and a low conversion gain reset signal is sampled from the floating diffusion node. The floating diffusion is set to high conversion gain and a high conversion gain reset signal is sampled from the floating diffusion node. Charge carriers are transferred from the photodetector to the floating diffusion node and a high conversion image signal is then sampled from the floating diffusion node. The floating diffusion is set to low conversion gain. Charge carriers are transferred again from the photodetector to the floating diffusion node and a low conversion image signal is sampled from the floating diffusion node.

Dual conversion gain high dynamic range sensor

An image sensor, readout circuitry for an image sensor, and a method of operating readout circuitry are disclosed. Readout circuitry includes an analog-to-digital-converter ('ADC') including input stage circuitry with a first selectable input and a second selectable input. The ADC is coupled to sequentially receive a first reset signal, a second reset signal, a high gain image signal, and a low gain image signal, in that order. The input stage circuitry is configured to select the first selectable input when receiving the first reset signal and the low gain image signal and select the second selectable input when receiving the second reset signal and the high gain image signal.

Compensation for dual conversion gain high dynamic range sensor

A tubing hanger () landing in a tubular element (), having a coupling assembly () for hydraulic coupling between the tubing hanger () and the element. A coupling element () moves radially between an outer coupled position and an inner non-coupled position. An actuation element () with a contact surface () exerts an outward actuation force onto an inner actuation surface () of the coupling element. The actuation element comprises two actuation sections () exposed to a outward force from an actuation arrangement (). The contact surface () has a distance the actuation sections. The actuation element moves in the radial outward direction so that the movement of at least one of the two actuation sections () stops after the radial movement of the contact surface () stops. The contact surface () movement halts as the coupling element () reaches the coupled position.

Tubing hanger with coupling assembly

An image sensor includes a pixel array having pixels arranged in rows and columns, a first successive-approximation-register ('SAR') analog-to-digital-converter ('ADC'), a second SAR ADC, and first and second control circuitry. The first SAR ADC includes a first capacitor array (&#x201c;FCA&#x201d;) that shares a first common terminal coupled to a first comparator and coupled to receive first analog pixel signals. The second SAR ADC includes a second capacitor array (&#x201c;SCA&#x201d;) that shares a second common terminal selectably coupled to a second comparator and coupled to receive second analog pixel signals. The first and second control modules are coupled to selectably switch bottom plates of the FCA from a low reference voltage to the high reference voltage at a same time as selectably switching bottom plates of the SCA from a high reference voltage to the low reference voltage.

Conversion circuitry for reducing pixel array readout time

A step-up converter includes an input coupled to receive a first voltage potential and an output coupled to output a second voltage potential higher than the first voltage potential. The step-up converter also includes an array of capacitance charge pumps. Each of the capacitance charge pumps in the array includes switches to be modulated to individually run each of the capacitance charge pumps by selectively connecting each of the capacitance charge pumps to the input and the output. The step-up converter further includes a control module coupled to the switches of each of the capacitance charge pumps and configured to modulate the switches at a substantially fixed frequency. The control module modulates the switches of selected capacitance charge pumps in the array in response to a current draw on the output. The step-up converter may be included in an image sensor.

Capacitance selectable charge pump

A novel image sensor includes a pixel array, a row control circuit, a test signal injection circuit, a sampling circuit, an image processing circuit, a comparison circuit, and a control circuit. In a particular embodiment, the test signal injection circuit injects test signals into the pixel array, the sampling circuit acquires pixel data from the pixel array, and the comparison circuit compares the pixel data with the test signals. If the pixel data does not correspond to the test signals, the comparison circuit outputs an error signal. Additional comparison circuits are provided to detect defects in the control circuitry of an image sensor.

System and method for sensor failure detection

A comparator including a preamplifier amplifying a first signal and a second signal to produce a first amplified signal on a first output terminal and a second amplified signal on a second output terminal. The comparator also includes a capacitor, a clamp and a latch coupled in parallel to the first output terminal and the second output terminal of the preamplifier. A control circuit is coupled to the variable capacitor and the clamp and is configured to close the clamp during a first time period to cause the first amplified signal and the second amplified signal to bypass the capacitor and the latch, and open the clamp during a second time period following the first time period to cause the first amplified signal and the second amplified signal to be coupled to the capacitor and the latch. The capacitor filters the amplified signals, and the latch produces a digital output signal of the comparator based on the filtered signals.

Comparator noise reduction by means of a programmable bandwidth

Imagers reproduce an image by converting photons to a signal that is representative of the image. A sensor readout module reads reset and signal voltages corresponding to a plurality of integration times for each of a plurality of pixels. The sensor readout module is capable of determining whether the differences between reset and signal voltages corresponding to respective integration times indicate a saturation condition of the pixel. Accordingly, the sensor readout module may provide an output signal based on reset and signal voltages corresponding to an integration time that is less than an integration time for reset and signal voltages that indicate the saturation condition. A normalization module may normalize the output signal to correspond with a linear response curve.

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Oslo, Norway

Robert Johansson