Nxp B.v.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Koninklijke Philips Corporation N.v.

Robert James Pascoe Lander

Gerben Doornbos

Casper Van Der Avoort

Thomas Merelle

Jozef Thomas Martinus Van Beek

Andreas Bernardus Maria Jansman

Dirk Maarten Knotter

Johannes Van Wingerden

Joep Bontemps

A FinFET whose fin has an upper portion doped with a first conductivity type and a lower portion doped with a second conductivity type, and the junction between the upper portion and the lower portion acts as a diode. The FinFET further includes: at least one layer of high-k dielectric material (for example SiN) adjacent at least one side of the fin for redistributing a potential drop more evenly over the diode. Examples of the k value for the high-k dielectric material are k&#x2267;5, k&#x2267;7.5, and k&#x2267;20.

Fin field effect transistor (FinFET)

A substrate arrangement comprising a substrate having a surface configured to receive, by epitaxy, an epitaxial layer of semiconducting material, the substrate comprising a laminate having a handle layer and a seed layer, the seed layer having a crystal orientation arranged to receive the epitaxial layer and the handle layer having a crystal orientation different to the seed layer.

Substrate arrangement

A resonator has a main resonator body and a secondary resonator structure. The resonator body has a desired mode of vibration of the resonator alone, and a parasitic mode of vibration, wherein the parasitic mode comprises vibration of the resonator body and the secondary resonator structure as a composite body. In this way, unwanted vibrational modes are quenched by the second suspended body.

Resonator

An integrated circuit comprising a MEMS (microelectromechanical system) element in a plane of the integrated circuit, the MEMS element being suspended in a cavity over a substrate, said cavity including a first cavity region in said plane spatially separating an edge of the MEMS element from a wall section, said edge being arranged to be displaced relative to the wall section; and a second cavity region in said plane forming part of a fluid path further including the first cavity region, said fluid path defining a first volume; and a third cavity region in said plane defining a second volume in fluid connection with the second cavity region, wherein the maximum width of the second cavity region is larger than the maximum width of the third cavity region, the second and third cavity regions having maximum widths that are larger than the maximum width of the first cavity region.

Integrated circuit with MEMS element and manufacturing method thereof

A method and circuit in which the drive strength of a FinFET transistor can be selectively modified, and in particular can be selectively reduced, by omitting the LDD extension formation in the source and/or in the drain of the FinFET. One application of this approach is to enable differentiation of the drive strengths of transistors in an integrated circuit by applying the technique to some, but not all, of the transistors in the integrated circuit. In particular in a SRAM cell formed from FinFET transistors the application of the technique to the pass-gate transistors, which leads to a reduction of the drive strength of the pass-gate transistors relative to the drive strength of the pull-up and pull-down transistors, results in improved SRAM cell performance.

FinFET drive strength modification

A crystalline semiconductor resonator device comprises two matched resonators which are aligned differently with respect to the crystal structure of the crystalline semiconductor. The resonators each comprise a portion of a material having a different temperature dependency of the Young's modulus to the temperature dependency of the Young's modulus of the crystalline semiconductor material. In this way, the suspension springs for the resonators have different properties, which influence the resonant frequency. The resonant frequency ratios between the first and second resonators at a calibration temperature and an operation temperature are measured. A frequency of one (or both) of the resonators at the operation temperature can then be derived which takes into account the temperature dependency of the one of the resonators.

MEMS resonators

The present disclosure provides various embodiments of a semiconductor device and method of fabricating the semiconductor device. An exemplary semiconductor device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate and a tuned, stressed metal gate layer disposed over the gate dielectric layer. The tuned, stressed metal gate layer includes a stress that distributes strain differently to portions of the semiconductor substrate having different surface characteristics. In an example, the gate stack is disposed over a portion of a fin of the semiconductor substrate, and the fin has a varying thickness, providing a fin with a roughened surface. The tuned, stressed metal gate layer includes a stress that distributes strain differently to portions of the fin having different thicknesses.

Semidonductor device having stressed metal gate and methods of manufacturing same

A resonator comprising a beam formed from a first material having a first Young's modulus and a first temperature coefficient of the first Young's modulus, and a second material having a second Young's modulus and a second temperature coefficient of the second Young's modulus, a sign of the second temperature coefficient being opposite to a sign of the first temperature coefficient at least within operating conditions of the resonator, wherein the ratio of the cross sectional area of the first material to the cross sectional area of the second material varies along the length of the beam, the cross sectional areas being measured substantially perpendicularly to the beam.

finFET drive strength modification

The present disclosure provides a semiconductor device and method of fabricating a semiconductor device. In an embodiment, the semiconductor device is a finFET device. In an embodiment, the semiconductor device is a silicon on insulator (SOI) device. A method of fabricating the semiconductor device includes providing a substrate, forming an oxide layer on the substrate, forming a fin on a portion of the oxide layer, forming a high k dielectric layer on a portion of the oxide layer and on a portion of the fin, forming a tuned, stressed metal gate on the dielectric layer, and forming a poly-cap on the metal gate. The method of fabrication provided may allow use of SOI substrate or bulk silicon substrates.

Method of fabricating a semiconductor device

A resonator having an effective spring constant (k) and comprising a beam having a beam spring constant (k) adapted to resonate in an oscillation direction, and extending at a non-zero angle (&#x3b8;) to the oscillation direction, wherein the resonator has a predetermined geometry and is formed from one or more materials, the or each material having a coefficient of thermal expansion (CTE), the CTE of the or each material together with the predetermined geometry of the resonator causing &#x3b8; to vary with temperature, such that the temperature dependence of the beam spring constant is compensated for, resulting in the effective spring constant of the resonator remaining substantially constant within an operating temperature range.

Consistent with an example embodiment according to the invention, a material for the intermediate layer is chosen which can be selectively etched with respect to the dielectric layer. Before the deposition of the first conductor layer, the intermediate layer is removed at the location of the first channel region, and after the deposition of the first conductor layer and the removal thereof outside the first channel region and before the deposition of the second conductor layer, the intermediate layer is removed at the location of the second channel region. Thus, field effect transistors (FETs) are obtained in a simple manner and without damage to their gate dielectric. Preferably, a further intermediate layer is deposited on the intermediate layer which can be selectively etched with respect thereto.

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Leuven, Belgium

Robert James Pascoe Lander