International Business Machines Corporation

Lockheed Martin Corporation

Robert James Lynch

Anthony Correale, Jr

Hyman David Chantz

Gerard M Salem

Robert R Livolsi

Elijah Swift

Andrew Zachary Glovatsky

Jay Robert Herring

Joseph M Hoke

Steven Louis Makow

Roy A Wood

George A Williams, Ii

Andrew Z Muszynski

Peter W Ziolkowski

James G Motto, Jr

Steve A Repchak

Brian Thomas Kindl

Jean M Vittone

Lawrence R Yetter

Links between multiple points are monitored. A determination is made that there is a change in power on a link being monitored. Based on determining that there is the change in the power on the link, latency on the link is checked and an anomaly on the link is detected. Based on detecting that there is the anomaly on the link, a determination is made of a type of the anomaly based on whether the checking indicates there is a latency change in the latency of the link.

Multi-modal monitoring of links between multiple points

The method provides for separable subchannels sharing a communication channel. A processor receives input of a user setting a transmitter device to a first of at least two subchannels of a communication channel in which the first subchannel comprises a first portion of a bandwidth of the communication channel. The processor receives an audio signal as input to the transmitter device. The processor converts a time-series waveform of the audio signal into a frequency-series waveform. The processor determines that the transmitter device is set to the first subchannel. In response to determining the device is set to the first channel, the processor filters the frequency-series waveform through a series of steep shoulder digital bandpass filters set to transmit through the first portion of the bandwidth, and the processor transmits the audio signal as the filtered frequency-series waveform.

Separable, intelligible, single channel voice communication

A flip-flop is disclosed. The flip-flop includes a first latch for receiving at least one bit and a second latch coupled to the first latch for storing the at least one bit from the first latch. The size of the second latch is minimized to reduce power consumption. The flip-flop also includes a multiplexor coupled to the first latch and to the second latch for outputting the at least one bit from the first latch, when a clock to the multiplexor is active and for outputting the at least one bit from the second latch when the clock is inactive. A system and method in accordance with the present invention optimize power consumption in a flip-flop through the use of a multiplexor for the output function. As a result, the size of the slave latch can be minimized, which reduces the overall power consumption of the device.

Method and circuit for optimizing power consumption in a flip-flop

A transmission line for carrying digital signals is provided with auxiliary line drivers at the receiver end, which are used in combination with the data line driver at the transmitting end to apply a sequence of sets of test voltages onto the line. The voltage resulting at the receiver input is used to detect open signal conductors and/or shorts in the receiver.

Method and apparatus for testing a signal line

A system and method of controlling the operation of a storage device (a semiconductor latch in its preferred embodiment) to reduce the power consumed by the storage device. The system uses a split clock signal to control the operation of the latch, with an early enable signal and a late enable signal being operable to turn the latch on when needed and to turn it off when it is not needed. More particularly, the present invention logically generates clocking control signals for the latch using the early enable signal and the late enable signal to control the operation of the latch and to reduce power consumption and allow for an increased period of time to make a decision whether to turn off the early enable signal. One clock input is generated from one of the enable signals and the other is a function of both of the enable signals and the redundant enable signal is used in an AND gate late in the generation of the clocking signal, thus using a redundancy in the enable signals to control one of the clock inputs and provide control of the storage device for an extended period of time.

Method and system for reducing power dissipation in a semiconductor storage device

A fixture for holding two members in alignment and in pressure engagement with each other during partial welding of the two members to each other and for holding the members in alignment and pressure engagement with each other while the two members are repositioned in the welding machine so the welding of the members to each other can be completed. The fixture includes a magnetic base for postionably mounting the fixture with respect to a welding unit, an extension extending from the magnetic base with the extension angularly supporting a lever spring in a cantilevered fashion with the free end of the cantilevered spring engaging a ball held in position by a magnetic holder. The ball is positioned above the members so that pressure engagement of the ball with the free end of the cantilevered spring maintains the two members in alignment and pressure engagement to enable the hermetic sealing of the two members to each other or to permit angular repositioning of the two members with respect to a welding unit without having to disturb the alignment and contact between the two members.

Low profile welding fixture

An adapter card in a computer system includes an application specific integrated circuit (ASIC) and a field programmable gate array (FPGA) coupled to the ASIC. Random data is provided to the ASIC logic function(s) by control of the FPGA, which is configured by a programmable logic device on the card and coupled thereto. The logic function(s) of the ASIC is then exercised with the random data, and the output is compared with expected output by the system to determine if there are any errors. The determination is made based on a signature produced by a multiple input shift register (MISR) within the ASIC, based on the output data from the logic function(s). The FPGA can then be reconfigured for normal adapter card functions.

Method for testing adapter card ASIC using reconfigurable logic

Apparatus for testing an adapter card ASIC with reconfigurable logic

Electrical characteristics of the inputs to VLSI semiconductor chips can be modified after the chips are fabricated and mounted into multichip modules (packages), at which time the required characteristics are known accurately. The changes are accomplished by incorporating special circuitry at the chip inputs during their design combined with the use of `boundary-scan` type circuitry that has recently been put in place for device testing. The circuitry allows the impedance characteristics of the chip's receiver to be modified to match that of the driving source and the wiring interconnections between the chip and source. The test circuitry is used to provide the logical signals to selectively switch the circuits to the proper configuration. This enables optimally designed interconnections between the input and output circuitry on the chips and thereby avoids the necessity for costly re-designs.

Logically configurable impedance matching input terminators for VLSI

A localized soldering station is described that uses the vapor phase reflow principle. A container has of a medium selected because of the temperature at which it changes to a vapor. A heated conduit maintains the vapor state while conveying the vapor to a work location where a module with a part to be removed or attached by solder connections is supported. A transparent, quartz nozzle confines the vapor to the part and its solder connections and is positioned accurately by a unit that includes a guide light. Vapor will lose its latent heat of vaporization upon contact with the part and its solder connections, causing the solder to reflow and change back to a liquid, which is collected for reuse. When in a standby or ready condition, vapor is conveyed up through a shutoff valve through cooling fins where it changes back to a liquid and returns to the container, avoiding loss.

Growing community of inventors

Raleigh, NC, United States of America

Robert James Lynch