Arm Limited

Robert James Catherall

David John Butcher

Rhys David Copeland

Jeremy Isle Johnson

Alasdair Grant

Anthony Neil Berent

Martyn Maurice Capewell

Peter James Horsman

Sanne Wouda

Mark Edgeworth

Jonathan Stephen Black

A method and computer program for generating code coverage information during testing of a code sequence are described, in which the code sequence comprises decisions, each having one or more conditions as inputs. The method includes executing the code sequence on target processing circuitry under the control of test stimuli and maintaining, in memory, a code coverage table for at least one decision. When a decision is evaluated, a bitstring is created within a storage element, each position in the bitstring being associated with one of the conditions and the value in that position representing the value of that condition used in evaluating the decision. The bitstring is used to identify the entry, in the code coverage table associated with the evaluated decision, for that combination of values of the conditions, and a confirmation value is recorded in that entry, indicating that the decision has been evaluated for that entry.

Generation of code coverage information during testing of a code sequence

There is provided execution circuitry. Storage circuitry retains a stored state of the execution circuitry. Operation receiving circuitry receives, from issue circuitry, an operation signal corresponding to an operation to be performed that accesses the stored state of the execution circuitry from the storage circuitry. Functional circuitry seeks to perform the operation in response to the operation signal by accessing the stored state of the execution circuitry from the storage circuitry. Delete request receiving circuitry receives a deletion signal and in response to the deletion signal, deletes the stored state of the execution circuitry from the storage circuitry. State loss indicating circuitry responds to the operation signal when the stored state of the execution circuitry is not present and is required for the operation by indicating an error. In addition, there is provided a data processing apparatus comprising issue circuitry to issue an operation to execution circuitry. The execution circuitry stores a stored state that is accessed during performance of the operation and error detecting circuitry detects an indication of an error from the execution circuitry that the stored state is required for performance of the operation and that the stored state has been deleted.

Execution circuits using discardable state

A trusted content usage monitor for monitoring content usage is provided. A unique identifier generation unit generates a unique identifier indicative of content being rendered and a packet generator generates a trusted packet comprising the unique identifier. The trusted packet is trust signed by the trusted content usage monitor, so that it can be trusted by its recipient. The trusted content usage monitor has at least one mode of operation in which content rendering cannot be decoupled from operation of the unique identifier generation unit, so that generated packets can be trusted as truly indicative of content usage.

Content usage monitor

Simulation of execution of a processing workload by a target hardware device is provided by providing workload data specifying the processing workload, passing the workload data to both a primary partial simulation and a complementary partial simulation that run in parallel and acquire input data from different levels of abstraction of the target hardware and then simulating execution of the processing workload using a primary partial simulation to generate primary partial result state data and using the complementary partial simulation to generate complementary partial result state data. The target hardware device may be a graphics processing unit and the workload data may specify the processing to be performed in a hardware independent form, such as, for example, OpenGL ES. The host system supporting the simulation may include a graphics processing unit serving to provide the complementary partial simulation due to its own execution of the workload data.

Hardware simulation

A data processing apparatus and method are provided for tracing activities of a shader program executed on shader circuitry of a data processing apparatus. The data processing apparatus comprises shader circuitry which is responsive to input data for a pixel to execute a shader program to generate a color value for the pixel. The shader program has multiple execution paths via which the color value may be generated, and which execution path is taken is dependent on the input data. An image buffer having a plurality of storage locations is provided, with each storage location being used to store the color value generated by the shader circuitry for an associated pixel. In a trace mode of operation, execution of the shader program by the shader circuitry causes a trace vector to be generated containing a plurality of items of execution path information indicative of the execution path taken, the trace vector comprising a plurality of fields, each field being used to store one item of execution path information. The trace vector as output is constrained to be of the same size as the color value, and in the trace mode of operation the trace vector is stored in one of the storage locations of the image buffer in place of the color value generated by the shader program. This has been found to provide an efficient mechanism for obtaining execution path data useful when performing a variety of debugging activities in respect of a shader program.

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Cambridge, United Kingdom

Robert James Catherall