Digital Equipment Corporation

Ericsson Gmbh

Ericsson Ab

Marconi Intellectual Property (ringfence), Inc.

Robert J Walsh

Walter Clark Milliken

Robert E Thomas

Bradley J Miller

Steve N Barbas

Cuneyt M Ozveren

Gregory Stephen Lauer

Andrew V Hoar

Todd Andrew Snide

Chase T Tingley

Greg Waters

James F Friend

Stephen D Glaser

A system for supporting translation of virtual IP addresses to Ethernet/MAC addresses in a multi-Virtual Network environment, in which address resolution tables are generated and maintained by Virtual Networking Devices. Virtual Networking Device (VND) sends and/or receives Virtual Network-specific ARP traffic. The Virtual Network-specific ARP traffic includes ARP requests or responses that map a MAC address to an IP address in the private IP address space of an associated Virtual Private Network. The disclosed Virtual Networking Devices can therefore operate in configurations in which multiple independent entities operate on separate Virtual Networks, and where servers may be accessible via virtual IP addresses within the private IP address spaces of associated Virtual Networks.

Extension of address resolution protocol (ARP) for internet protocol (IP) virtual networks

A method for performing rate policing and re-marking in a packet switched communications network that can be used to enforce and/or monitor Class of Services (CoS) contracts including terms for single or multiple classes of service. A switching system configured as an ingress node on the network includes a network switch and rate policing and re-marking logic. The switch receives a data packet transmitted on the network, extracts information from at least one header field of the packet including a CoS parameter, a primary flow ID established for the packet, and a packet byte count, and provides the extracted information to the rate policing/re-marking logic. Next, the rate policing/re-marking logic performs flow record and token bucket processing on the primary packet flow to determine whether the packets of the primary flow conform to the bandwidth requirements specified in the CoS contract. In the event the primary flow is a sub-flow of an aggregated packet flow, the logic also performs flow record and token bucket processing on the aggregated flow to determine whether the packets of the aggregated flow comply with the terms of the CoS contract. The logic then provides the token bucket processing results to the switch. Based on these results, the switch may pass the packet unmodified on the network, pass the packet re-marked with a new CoS on the network, or drop the packet from the network.

Dual use rate policer and re-marking logic

A system and method for configuring a control plane within a network device. One of a pair of control processors is selected to act as the master of the control plane and the other control processor is specified as a standby control processor in normal operation. In the case of a failover or switchover event, the standby control processor assumes the role of the master of the control plane and updates configuration information within line cards in the network device as necessary. A state machine within the control processor is employed to manage state transitions for the control processor. Each control processor generates at least one signal that indicates whether it is capable of serving as the master of the control plane. Master selection logic selects one of the control processors as the master for the control plane and in one embodiment advertises the identification of the master control processor via triply redundant signals. Voting logic within the control processors and other cards within the network device is employed to identify the selected master unit for the control plane. The selected master control plane processor forwards the configuration information over control paths that are isolated from the data path within the network device.

Method and system for selecting a master controller in a redundant control plane having plural controllers

A language construct that allows a software programmer to use an intermediate or high-level language command to explicitly group operations or fuse loops in a group of statements operating on parallel arrays is disclosed. The command instructs a compiler, which would otherwise add temporary variables to avoid data dependencies or perform data dependency analysis, to translate the enclosed statements directly into machine language code without adding those temporary variables and without performing any data dependency analysis. Execution of the command results in the performance of the group of statements by all of the virtual processors.

Parallel processing system for virtual processor implementation of

Postponing the interrupt for an I/O event can increase system throughput by amortizing the cost of the interrupt service routine over multiple I/O events. In current systems that provide interrupt postponement, the time parameter is fixed. Fixed values can lead to parameter configuration errors, excessive characterization work to generate parameter values, and a failure to automatically re-configure to system changes or to external load changes. The proposed mechanism measures actual system experience and eliminates the parameter configuration effort by filtering its own experience to derive a target value for interrupt postponement. A current postponement value with the potentially greater variance than the target is used to rapidly respond to abrupt change in offered load. The invention also benefits tasks with real-time deadlines to provide correct system operation.

Adaptive mechanism for efficient interrupt processing

In the present invention, one of the bits in the tag value in the cache is hard-wired, for example, to 0, at such a position in the cache that that bit is always set to 0 when a tag is stored in the cache (or forced to 0 when a tag is read from the cache). Instructions executed by the processor can specify a read outside the cache, i.e. of the most recent data written to the main memory by some DMA agent, by specifying a read address with the designated bit equal to one. In this way, a cache miss is forced, allowing the processor to read the most recent data from the main memory of the system and to cache the data. As the cache is refilled from the main memory, the hard-wired tag bit of course remains set to zero. So later processor instructions that read data within the same cache refill block would use the normal address of that data (having the designated bit set to zero). These subsequent reads will not force a cache miss. Instructions executed by the processor can flush the cache by reading a sequence of addresses in which the designated tag bit is one. Since the designated bit is 0 in all cache tags, there will be misses on all words, so the entire cache will be filled from the main memory.

Method and apparatus for efficient cache refilling by the use of forced

In an interactive video-on-demand system, real-time programs are encoded as a transport stream including a plurality of transport stream packets. Some of the transport stream packets include timing signals indicating the real time of the program. The transport stream packets are formatted into transport cells for transport over an asynchronous transfer mode network from a source to a destination. The cells are transported at a transport rate which is determined by a network clock. The transport rate is chosen to deliver the transport stream faster than the real time of the program. While transporting the transport stream, it is determined if the transport stream is being transported ahead of the real time of the program. In this case, idle cells are injected into the transport stream to have the program arrive at the destination in the real time of the program.

Growing community of inventors

Ashland, MA, United States of America

Robert J Walsh