Dell Products Inc.

Hewlett-packard Development Company, L.P.

Hewlett Packard Enterprise Development LP

Compaq Information Technologies Group, L.p.

Robert J Volentine

Dirie N Herzi

Juan Francisco Diaz

Frank L Wu

Mark A Piwonka

Vijay Bharat Nijhawan

Robert C Elliott

Madhusudhan Rangarajan

Louis B Hobson

Mark W Shutt

Krishnaprasad Koladi

Bi-Chong Wang

Patrick L Gibbons

Kiran Kumar Devarapalli

Rahul Patel

Viratkumar Maganlal Manvar

Natalie Quach

Jagadeesha Bollandoor

Peter Cloney

In one example in accordance with the present disclosure, a system for handling memory errors includes a memory module having volatile components and non-volatile components. The system includes a BIOS chip having BIOS code and a BIOS non-volatile (NV) memory. The BIOS NV memory stores error data associated with the memory module that was stored prior to a power-on or reset of the system. The system includes a processor to execute the BIOS code to, after the power-on or reset of the system end before an operating system is loaded; (1) read, from the BIOS NV memory, the error data; and (2) determine, based on the error data, whether to take a corrective action with respect to the memory module.

Handling memory errors in memory modules that include volatile and non-volatile components

In one example in accordance with the present disclosure, a device comprising a host computing device further comprises a processor, a non-volatile dual inline memory module (NVDIMM) comprising metadata indicating system configuration information associated with the NVDIMM, and a basic input output system (BIOS) comprising system configuration information associated with the host computing device. The BIOS may: determine whether there is a mismatch between the system configuration information of the host computing device and the system configuration information indicated by the metadata.

NVDIMM metadata

Systems and methods are provided that may be employed to dynamically and intelligently allocate fault resistant memory (FRM) by calculating the currently required size of a protected reliable memory region for the FRM on an as-needed basis, rather than on a static basis. In one example, an operating system, or hypervisor or other virtualization layer may be employed to calculate the required size for the protected reliable memory region of the FRM based on current memory requirements of the virtualization layer kernel and running instances of other critical processes, and then to interact in real time with the system BIOS to cause an adjustment in the reserved protected reliable memory region.

Systems and methods for dynamic memory allocation of fault resistant memory (FRM)

A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, determine whether to exit the entry synchronization loop after the timeout value has been reached.

Processor interrupt command response system

Systems and methods for reducing problems and disadvantages associated with physically asymmetrical memory structures are disclosed. A method for configuring memories in an information handling system having a plurality of memories, each memory local to one of a plurality of nodes, and wherein at least one memory of the plurality of memories has a different memory capacity than at least one other memory of the plurality of memories is provided. The method may include determining a smallest memory capacity of the plurality of memories. The method may also include allocating a node-interleaved memory using a portion of each memory equal to the smallest memory capacity. For each particular memory not fully allocated to the node-interleaved memory, each portion of each particular memory not allocated to the node-interleaved memory may be associated with a node local to the particular memory.

System and method for memory architecture configuration

A system to perform an information handling system (IHS) initialization includes one or more subsystems to receive a command to power on the IHS, initialize a processor cache memory to emulate a random access memory (RAM), determine whether a manufacturing self test is being performed on the IHS, and in response to the manufacturing self test being performed, complete the initialization without a complete memory initialization.

Self test initialization

A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, and determine whether to exit the entry synchronization loop after the timeout value has been reached.

Synchronizing processors when entering system management mode

A system and method of a basic input output system (BIOS) test system are disclosed. According to an aspect, a basic input output system (BIOS) test system can include a BIOS test manager configured to enable BIOS testing of multiple information handling systems within a test environment. The BIOS test system can also include a local test harness driver operable to be coupled to the remote BIOS test manager to receive test routines, and a test buffer configured to receive a test routine from the BIOS test manager. The test routine can further be executed using a test engine integrated as a part of a BIOS of a particular information handling system.

System and method of managing BIOS test routnes

A method according to the invention ensures optimal memory configuration in a computer: A determination is made whether performance can be improved by rearranging the DIMMs that are installed in the computer. If so, then a user of the computer is notified that the DIMMs can be rearranged to improve performance.

Method for ensuring optimal memory configuration in a computer

In one embodiment a method comprises collecting device configuration information during an initialization process in a computing device, storing the device configuration in a memory buffer, and using the device configuration information to restore the computing device from a low-power mode to an operational mode.

Sleep state resume

Client software stores an identifier corresponding to memory configuration data of interest and causes a software interrupt that requests a memory configuration read function. An interrupt read function handler then reads the data of interest responsive to the identifier and returns the data of interest. The client software may include, for example, BIOS firmware or application software executing in real or protected mode. The memory configuration information may be stored in a hidden I/O or MMIO register device. In such an embodiment, the interrupt handler may enable access to the hidden I/O or MMIO register device prior to reading the data of interest and disable access to the hidden I/O or MMIO register device afterwards.

Providing access to memory configuration information in a computer

A computer system that simulates a memory stack in a non-general purpose register set in the computer's CPU. The computer system can use the simulated memory stack to store a return address before jumping to a subroutine or use the simulated stack to store a data value for subsequent retrieval and use. The non-general purpose register set may include memory type range registers (MTRRs). One of the MTRRs is designated as the stack pointer register and is used to store a pointer index value which identifies which of the other MTRR registers is associated with the top of the simulated memory stack. The computer system preferably includes a non-volatile memory, such as a ROM, which contains executable instructions for implementing the simulated memory stack. The instructions provide for incrementing and decrementing the pointer index value and writing to and reading from the MTRR registers identified by the pointer index as associated with the top of simulated stack. By using non-general purpose registers to store data and return addresses, more general purpose registers are available for other reasons. The computer system advantageously permits the simulation of a conventional memory stack when main memory is not available to provide the conventional memory stack.

Growing community of inventors

Round Rock, TX, United States of America

Robert J Volentine