Qualcomm Incorporated

USA As Represented by Secretary of the Navy

Robert J Vachon

Keith Alan Bowman

Daniel Yingling

Yimai Peng

Jeffrey Alexander Levin

Venkat Rangan

Prajakt Kulkarni

Nidish Ramachandra Kamath

Curtis Drew Musfeldt

Satish Goverdhan

Alex Jong

Srivatsan Srinivasan

Luis S Kida

Rod A McLennan

Robert M Anderson

Wayne G Wilson

Kenneth W Dickey

Perry W Crutchfield

An apparatus, including: a first flip-flop including a scan input configured to receive a scan signal, a clock input configured to receive a first clock signal of a first clock domain; a latch including an input coupled to an output of the first flip-flop, a clock input configured to receive a control signal; and a second flip-flop including a scan input coupled to an output of the latch, a clock input configured to receive a second clock signal of a second clock domain, and an output configured to generate the scan signal, wherein at least one of the first or second flip-flop comprises a first dual-edge-triggered (DET) flip-flop.

Lock-up latch for dual-edge-triggered flip-flops

An apparatus, including: a clock gating circuit (CGC), including: a clock gating device configured to selectively gate/pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit configured to select a non-complementary clock signal or a complementary clock signal to generate the selected clock signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal.

Clock gating circuit for dual-edge-triggered flip-flops

Certain aspects of the present disclosure provide techniques for time management and scheduling of synchronous neural processing on a cluster of processing nodes. A slip (or offset) may be introduced between processing nodes of a distributed processing system formed by a plurality of interconnected processing nodes, to enable faster nodes to continue processing without waiting for slower nodes to catch up. In certain aspects, a processing node, after completing each processing step, may check for received completion packets and apply a defined constraint to determine whether it may start processing a subsequent step or not.

Method and apparatus for time management and scheduling for sychronous processing on a cluster of processing nodes

Embodiments of methods, apparatuses, devices and systems associated with combining or mixing digital media streams are disclosed.

System, method or apparatus for combining multiple streams of media data

A circuit card assembly is provided for use in testing a system wherein the circuit card assembly employs a surface mount device such as a field programmable gate array. The circuit card assembly includes severable traces on a bottom surface of the assembly connecting pairs of near and far vias. The severable traces and the pairs of near and far vias allow the circuit card assembly to be selectively re-worked to accommodate changes to the design of the surface mount device. Hence, a new circuit card assembly need not be designed and fabricated each time the design or programming of the surface mount device is changed. The circuit card assembly includes a network of interconnection paths wherein each path to or from a pin terminal area of the circuit card assembly passes along at least one severable trace between at least one pair of near and far vias along the bottom surface of the assembly. Hence, any selected interconnection path to or from a terminal area can be broken, if desired, by severing the bottom surface trace of the selected path. Likewise, new interconnection paths can be added, if desired, between any two pre-existing paths to or from a terminal area by connecting jump wires along the bottom surface of the assembly between any two appropriate vias. Thus, re-working of interconnection paths of the circuit card assembly, perhaps to accommodate reprogramming of the surface mount device, is made much easier. Moreover, the chances that a re-programming of the surface mount device can be accommodated by re-working, rather than by fabricating a new circuit card assembly, is significantly enhanced.

Circuit card assembly footprint providing reworkable interconnection

A method and apparatus for presenting elevation angle information with rect to overhanging objects to an operator of a submersible incorporates a substantial portion of the sonar equipment found onboard conventional submersibles. Reflections of radiant energy from the objects are received by a highly directional array of hydrophones. The received reflections are time varying gain attenuated to substantially compensate for range-dependent signal variations such as are due to changes in scattering areas, spreading loss and attenuation loss. Using time varying gain processing and by taking into account the known directivity pattern of the hydrophones, the received reflections are reduced to represent signal characteristics due substantially to the elevation angle of the incoming reflections. These modulated reflections are quantized by first sorting the reflections into bands according to amplitude intensity and then by assigning a distinct color to the individual bands. The quantized reflections are then converted into color display signals according to their assigned colors, and the signals are displayed upon a color visual display to reveal object elevation angle information as distinct shades of color.

Color sonar for underwater object collision avoidance

Growing community of inventors

El Cajon, CA, United States of America

Robert J Vachon