Gte Automatic Electric Laboratories Incorporated

Robert J Tracey

Ronald J Violet

Alberto Boleda

Stevan D Bradley

Thomas E Clark

William F Hartley

A circuit arrangement for combining a measure of the single phase error for a received data signal in a PSK demodulator with a measure of the direction of rotation of the receive data signal phasor between adjacent sample times for producing a timing phase error signal for controlling the phase of a local clock timing signal in the demodulator. In a demodulator producing a digital word defining differences between the phases of decoded phasors at adjacent sample times, a binary bit D.sub.k of the digital word may define the direction of rotation of the received signal phasor between the adjacent sample times. Sample values of the signal phase error signal in the demodulator are quantized into single binary bits E.sub.k indicating the sense of the signal phase error at sample times. In one circuit arrangement, binary bits E.sub.k and D.sub.k are combined in an exclusive-OR gate for producing a binary timing phase error bit M.sub.k. In a demodulator where phase differences are consecutively numbered clockwise in straight binary, the output of the exclusive-OR gate is inverted for producing binary timing phase error bits M.sub.k. In another circuit arrangement, binary bits A.sub.k and B.sub.k indicating the sense of the in-phase and quadrature-phase signal components for decoded phasors at a number of sample times are logically combined with signal phase error bits E.sub.k for producing binary timing phase error bits M.sub.k at sample times.

Method and apparatus for generating timing phase error signals in PSK

An analog-to-digital converter employing a sample-hold, ramp generator and comparator in the conversion process combines the sample-hold and integrate functions in one operational amplifier. Provision may be made to derive the reference voltage, for the ramp generator, from the analog signal whereby automatic gain control is also obtained.

Analog-to-digital converter using common circuitry for sample-and-hold

An incoherent adaptive transversal equalizer for the receiver of a differentially phase-modulated data transmission system wherein a pair of tapped delay lines are located in memory of a digital computer or central processor which performs equalization of a sampled data signal according to the mean-square error algorithm defined by equations (1) - (4). In-phase and quadrature-phase tap gains c.sub.-.sub.n and d.sub.-.sub.n are each selectively combined with both the in-phase and quadrature-phase sampled signal component words A.sub.k.sub.+n and B.sub.k.sub.+n, respectively, at associated tap lines of the delay lines (except the principal or center tap line, where n = 0 here) to produce a plurality of weighted tap signals c.sub.-.sub.n A.sub.k.sub.+n ; -d.sub.-.sub.n B.sub.k.sub.+n ; c.sub.-.sub.n B.sub.k.sub.+n, and d.sub.-.sub.n A.sub.k.sub.+n. These weighted tap signals and the center tap line signals A.sub.k.sub.+0 and B.sub.k.sub.+0 are selectively combined to produce equalized in-phase and equalized quadrature-phase sampled signal component words A.sub.k ' and B.sub.k ' that are defined by equations (5) and (6). These equalized component words A.sub.k ' and B.sub.k ' of a current signal sample are operated on to obtain an indication .DELTA..theta. of the actual difference between phases of the current (k.sup.th) and prior (k-1.sup.th) signal samples. Common error signals AE.sub.k ' and BE.sub.k ' are produced during a current symbol interval by subtracting the in-phase and quadrature phase components of the k-1.sup.th equalized signal sample vector (A.sub.k.sub.-1 ', B.sub.k.sub.-1 '), after this vector is rotated by the phase angle .DELTA..theta., from the equalized in-phase and quadrature-phase components A.sub.k ' and B.sub.k ', respectively, of the current (k.sup.th) signal sample (see equations (3) and (4)). The products of the in-phase and quadrature-phase sampled signal component words A.sub.k.sub.+n and B.sub.k.sub.+n at associated tap lines of the delay lines, except the principal tap lines, where n = 0 here, and associated common in-phase and quadrature-phase error signals AE.sub.k ' and BE.sub.k ', respectively, are combined during a current symbol interval to produce values of the in-phase incremental tap gains .DELTA.c.sub. .sub.-n in equation (1). Tap gains c.sub.-.sub.n (where n .noteq. 0) that are obtained during a prior signal sample are combined during a current symbol interval with the new incremental tap gains .DELTA.c.sub.-.sub.n to obtain updated values of tap gains c.sub.-.sub.n for use during the next symbol interval, a principal tap gain here being the constant c.sub.o = 1. Also, the products of these component words A.sub.k.sub.+n and B.sub.k.sub.+n at each tap line of the delay lines, except the principal tap, where n = 0 here, and associated quadrature-phase and in-phase error signals BE.sub.k ' and AE.sub.k ', respectively, are combined during a current symbol interval to produce new values of the quadrature-phase incremental tap gains .DELTA.d.sub.-.sub.n in equation (2). Tap gains d.sub.-.sub.n (where n .noteq. 0) that are obtained during a prior signal sample are combined during the current symbol interval with the new incremental tap gains .DELTA.d.sub.-.sub.n to obtain updated values of tap gains d.sub.-.sub.n for use during the next symbol interval, the other principal tap gain here being the constant d.sub.o = 0.

Method and apparatus for incoherent adaptive mean-square equalization of

The input waveform is applied via an input resistor to the inverting input of an operational amplifier. The non-inverting input is grounded. In the preferred embodiment, two feedback networks, each comprising a diode and resistor network, are connected between the output and the inverting input of the amplifier. The diodes are oppositely poled. A capacitor is connected to ground at one end and to a charging resistor at the other. The other end of the charging resistor is connected to a junction formed by the resistor and diode in one of the feedback loops. The charging resistor is selected so that the value of the voltage for the reference which is supplied by the voltage across the capacitor C, e.sub.c, is of the value to obtain the percentage clipping desired. A discharge resistor is selected so that the capacitor and discharge resistor has a long time constant with respect to the input frequency of the waveform. The ratio of the resistor in the resistor diode feedback path which supplies the charging current to capacitor C to the resistance of the input resistor provides the constant percentage ratio of the clipper.

Constant percentage clipping circuit

A digital phase detector which periodically detects the phase angle .theta..sub.k of a carrier signal in which data are encoded as discrete phase changes. A coherent or differential phase-modulated carrier signal is split into its in-phase and quadrature phase components R.sub.o Sin.theta.(t) and R.sub.o Cos.theta. (t). Each signal component is sampled at a predetermined modulation interval and converted into a digital word having the form R.sub.o Cos.theta..sub.k and R.sub.o Sin.theta..sub.k. In one configuration, the two signal components are applied to a digital divider network which forms the quotient .PSI. of the two digital words such that .vertline..PSI..vertline..ltoreq. 1. The quotient .PSI.is applied to a data look-up ROM, programmed for Tan.sup.-.sup.1 operation, which forms a digital reference phase angle .PHI.limited to an angle .ltoreq. 45.degree. is corrected by selection logic to form the desired phase angle .theta..sub.k. Once .theta..sub.k is known for each modulation interval, the encoded data may be readily extracted, since .theta..sub.k is proportional to the encoded data.

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San Mateo, CA, United States of America

Robert J Tracey