Qualcomm Incorporated

Robert J Simpson

Jukka-Pekka Arvo

Petri Olavi Nordlund

Andrew Evan Gruber

Chun Yu

Alexei Vladimirovich Bourd

Colin Christopher Sharp

Aleksandra L Krstic

This disclosure describes techniques for extending the architecture of a general purpose graphics processing unit (GPGPU) with parallel processing units to allow efficient processing of pipeline-based applications. The techniques include configuring local memory buffers connected to parallel processing units operating as stages of a processing pipeline to hold data for transfer between the parallel processing units. The local memory buffers allow on-chip, low-power, direct data transfer between the parallel processing units. The local memory buffers may include hardware-based data flow control mechanisms to enable transfer of data between the parallel processing units. In this way, data may be passed directly from one parallel processing unit to the next parallel processing unit in the processing pipeline via the local memory buffers, in effect transforming the parallel processing units into a series of pipeline stages.

Computational resource pipelining in general purpose graphics processing unit

The example techniques described in this disclosure may be directed to interaction between a graphics processing unit (GPU) and a system memory. For example, the GPU may include a memory copy engine that handles tasks related to accessing data that is stored or is to be stored in the system memory. In addition, in some examples, the memory copy engine may perform additional tasks such as modification tasks to increase the performance of the GPU.

Memory copy engine for graphics processing

Aspects of the disclosure relate to a method of controlling a graphics processing unit. In an example, the method includes receiving one or more tasks from a host processor, and scheduling, independently from the host processor, the one or more tasks to be selectively executed by a shader processor and one or more fixed function hardware units, wherein the shader processor is configured to execute a plurality of instructions in parallel, and the one or more fixed function hardware units are configured to render graphics data.

Graphics processing unit with command processor

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Espoo, Finland

Robert J Simpson