3m Innovative Properties Company

Robert J Schubert

William Jeffrey Clatanoff

Hideo Yamazaki

Yusuke Saito

Gayle R T Schueller

Hideaki Yasui

Michael Albert Haase

Donald J McClure

Jens Weichold

Carl J Wentzel

Jeffrey H Tokie

William L Taylor

Andrew C Lottes

Christopher J Evoniuk

Terry F Hayden

Nga K Nguyen

Michael W Bench

Grace L Ho

Lora C Bonser

Donald J Mcclure

A tubular stress control article having an axial bore with a length comprises a first and innermost layer formed from an electrical stress control composition having a filler material comprising nanosilica-modified inorganic particles and a discontinuous arrangement of conductive material dispersed in an elastomeric material. At least a portion of the conductive material is in durable electrical contact with the inorganic particles. The article further comprises a second layer disposed on the first layer, the second layer comprising an electrical insulation material. The article also comprises a third layer disposed on the second layer, the third layer comprising an elastomeric stress control material. The article further comprises a fourth layer disposed on the third layer, the fourth layer comprising a track-resistant elastomeric material. Each of the first, second, third, and fourth layers are substantially continuous along the length of the axial bore.

Multilayer stress control article and dry termination for medium and high voltage cable applications

A cold-shrink article having a chamber with an enlarged interior section to prevent the collapse of an end of a support core placed in the chamber.

Cold-shrink separable connector

A process for forming gate structures is described. A web comprises a substrate, a plurality of conductive elements disposed on the substrate, and a conductive anodization bus. The web is moved through an anodization station to form a plurality of gate structures comprising a plurality of gate dielectrics adjacent to a plurality of gate electrodes. A process for forming electronic devices further providing a semiconductor, a source electrode, and a drain electrode is described.

Method for forming gate structures

A circuit includes a substrate having a dielectric layer with a first surface and a second surface. A conductive layer is formed on the first surface. A beveled via is formed in a dielectric layer of the substrate. The via has a first opening of a first width in the first surface, and a second opening of a second width in the second surface, the second width being greater than the first width. A conductive plug is connected to the conductive layer. The plug is formed in the via and extends from adjacent the first opening toward the second opening, and terminates adjacent the second opening at a plug interface surface. A conductive solder ball is connected to the plug interface surface and extends to protrude from the second surface.

Via plug adapter

A printed circuit including a dielectric substrate and a conductive trace attached to a surface of the dielectric substrate. The trace includes a base layer and a coverplate layer on a portion of the base layer. The coverplate layer defines a coverplate edge on the base layer. A protective layer is formed on a portion of the coverplate layer. The protective layer extends beyond the coverplate edge onto at least a portion of the base layer of the trace. A key aspect of the present invention is that the protective layer overlaps the coverplate edge of each trace to reduce the potential for corrosion of the base layer at the coverplate edge.

Flexible circuit with coverplate layer and overlapping protective layer

Growing community of inventors

Cedar Park, TX, United States of America

Robert J Schubert