International Business Machines Corporation

Robert J Savaglio

Masayuki Hayashi

Peter Albert Twombly

Richard F Keil

A process sort test circuit and methodology for determining performance characteristic of an IC chip. The circuit is located on an IC chip itself and comprises an input for receiving an input signal; a first path from the input to a first output for transmitting the input signal to the first output, the first path sensitive to variations in a manufacturing process for the IC chip; a second path from the input to a second output for transmitting the input signal to the second output, the second path being substantially less sensitive to the variations in the manufacturing process for the IC chip; and, a pulse generator device coupled to the first and second outputs for detecting a difference in arrival times of the input signal at the first and second outputs and for outputting a sort signal if the difference is of a preselected magnitude. The sort signal enables output indication of a performance characteristic of the IC chip.

On-demand process sorting method and apparatus

A shared path phase detector and phase indicator circuit provide a phase locked loop circuit for which loading and wiring dependencies are greatly reduced. The phase detector circuit is provided for receiving a reference clock and a second clock. The phase detector circuit provides a separate and unique signal for indicating the magnitude of the difference between the phase of the reference clock and the second clock, regardless of whether the second clock is leading or lagging the first clock. The phase indicator circuit detects whether the second clock is leading or lagging the first clock, and routes the pulses on a first internal signal path to generate either increment or decrement pulses depending on whether the second clock is lagging or leading, respectively. The generation of the increment and decrement pulses is also routed on the first internal signal path, which provides a phase locked loop circuit that does not require matched loading and custom wiring on the internal increment and the decrement paths as required in the prior art.

Shared path phase detector having phase indicator

A shared path phase detector circuit for receiving a reference clock and an oscillator clock, the phase detector circuit providing an output signal for indicating a magnitude difference between a phase of the reference and oscillator clocks. The output signal is independently derived from the leading or lagging edge relationship of the reference and oscillator clocks. The output signal does not describe which signal leads, but only the width magnitude difference. The design provides a single path over which the output signal travels, without feedback, such that the circuit dependencies are greatly reduced.

Shared path phase detector

A processing pulse control circuit for use in treating indeterminate signature increments in an apparatus producing RPT signature analysis of digital circuits. A circuit to control clock pulses to processing devices is provided. The circuit includes a counter to produce a count corresponding to the number of clock pulses received, and also a memory which stores clock count values where indeterminate signature increments will be encountered. A comparator compares the actual clock count values with the stored clock count values to produce a control signal. In response to this control signal, clock pulses are normally allowed to pass to a processing device during clock pulse counts at which determinate signature increments are encountered, but are blocked where indeterminate signature increments are encountered.

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Jericho, VT, United States of America

Robert J Savaglio