Intel Corporation

International Business Machines Corporation

Ampere Computing LLC

Sequent Computer Systems, Inc.

Robert J Safranek

Robert G Blankenship

Debendra Das Sharma

Robert H Beers

Jeff Willey

Jeffrey Charles Swanson

Aaron T Spink

Robert A Maddox

Venkatraman Iyer

Arvind A Kumar

Raj K Ramanujan

Yen-Cheng Liu

Simon P Johnson

Herbert H Hum

Darren S Jue

Ashish Gupta

Vedaraman Geetha

Bahaa Fahim

Fulvio Spagna

Rahul R Shah

James R Vash

Sitaraman V Iyer

Selim Bilgin

William Harry Nale

Ching-Tsun Chou

Abhishek Das

Yuvraj S Dhillon

Thomas D Lovett

Shaun M Conrad

Mahesh U Wagh

Zuoguo Wu

Gerald S Pasdast

Bruce Michael Gilbert

Ananthan Ayyasamy

Phanindra Mannava

Sandeep Brahmadathan

Meenakshisundaram Chinthamani

Hari K Nagpal

Aimee D Wood

Matthew Robert Erler

Robert J Toepfer

Xiaobei Li

Shailendra Ramrao Chavan

Jonglih Yu

Robert T Joersz

Mahesh S Natu

Eric N Lais

Kai Cheng

Ganapati Srinivasa

Donald R DeSota

Luke L Chang

Zhong-Ning George Cai

Ramacharan Sundararaman

Michelle M Sebot

Tracey L Gustafson

Kenneth Frank Dove

Xiaobel Li

Michael A Driscoll

Vincent G O'Malley

Richard L Coulson

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

High performance interconnect

In a processing system, a conversion circuit coupled to a system bus generates a flow control unit (FLIT) and provides the FLIT to a link interface circuit for transmission over an external link. The external link may be a peripheral component interface (PCI) express (PCIe) link coupled to an external device comprising a cache or memory. The conversion circuit generates the FLIT, including write information based on the write instruction, metadata associated with at least one cache line, and cache line chunks, including bytes of a cache line. The cache line chunks may be chunks of one of the at least one cache line. Including the metadata in the FLIT avoids separately transmitting the at least one cache line and the metadata over the external link, which improves performance compared to generating separate transmissions. In some examples, the FLIT corresponds to a compute express link (CXL) protocol FLIT.

Devices transferring cache lines, including metadata on external links

The system or device may build one or more data packets by dividing a given payload for a packet into data blocks and inserting data checks for each data block sequentially into the packet payload. The device may generate, for each of the data blocks, a corresponding data check block corresponding to data in each data block. The device may send or arrange the data blocks and the corresponding data check blocks such that each of the data blocks is followed by the corresponding error check block in the packet. Using the corresponding check block, each of the data blocks is independently verifiable, so that the data blocks may be used upon receipt, even if the payload is not completely received.

Method and system for sequencing data checks in a packet

Methods, apparatus, and systems, for transporting data units comprising multiple pieces of transaction data over high-speed interconnects. A flow control unit, called a KTI (Keizer Technology Interface) Flit, is implemented in a coherent multi-layer protocol supporting coherent memory transactions. The KTI Flit has a basic format that supports use of configurable fields to implement KTI Flits with specific formats that may be used for corresponding transactions. In one aspect, the KTI Flit may be formatted as multiple slots used to support transfer of multiple respective pieces of transaction data in a single Flit. The KTI Flit can also be configured to support various types of transactions and multiple KTI Flits may be combined into packets to support transfer of data such as cache line transfers.

Multiple transaction data flow control unit for high-speed interconnect

Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

Multichip package link

Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.

High performance interconnect link layer

A coherence protocol message is sent corresponding to a particular cache line. A potential conflict involving the particular cache line is identified and a forward request is sent to a home agent to identify the potential conflict. A forward response can be received in response to the forward request from the home agent and a response to the conflict can be determined.

High performance interconnect coherence protocol resolving conflict based on home transaction identifier different from requester transaction identifier

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Portland, OR, United States of America

Robert J Safranek