Other

Bull Hn Information Systems, Inc.

Honeywell Information Systems Inc.

Honeywell Bull, Inc.

Robert J Russell

Robert C Beauchesne

Robert W Romeri

A method and apparatus allows controlling a plurality of test operations in an electronic device, and in particular a volatile or non-volatile memory device in which a test mode has already been established, without the need for additional device connections. One such operation may be switching device operation from test mode to functional mode, the normal operating mode of the device. Other test operations include support of continuity testing by external circuitry, support of externally accessing device identification with which the device has been previously programmed, support of built in self-test, support of self-repair and support of other operations determined as needs arise.

Method and apparatus for controlling operating modes of an electronic device

A method and apparatus allows externally selecting a functional operation mode or one of a plurality of test operation modes of an electronic device, and in particular a volatile or non-volatile memory device, without the need for additional device connections. One variation of the method and apparatus allows unlimited switching between modes. Another variation of the method and apparatus limits test operation mode selection except at the time of powering up of the device. In either variation, mode selection is based on internally detected stimulus externally applied to the device that would not be present during normal functional operation of the device. Operation of the present invention is essentially transparent in applications where test operations are not utilized, making a device incorporating the present invention compatible with previous versions of the device where the present invention and test operation modes, such as IEEE P1581 and BIST, were not included.

A method and apparatus allows an electronic device to operate, first, in a test mode and, second, in a functional mode, the functional mode being the normal operating mode of the device. In the test mode, input stimulus is processed by test circuitry to control device outputs according to a relatively simple algorithm suitable for test purposes. When the device is in test mode, the functional circuitry reacts to the input stimulus in the same manner it would when the device is in functional mode. However, when the device is in test mode the functional circuitry does not control the device outputs. During this time the functional circuitry is in an undefined state, as would be expected immediately after power application. When predefined input stimulus is applied to the device which could cause part of the functional circuitry to switch to a defined state, test mode is deactivated and functional mode activated. When so activated the functional circuitry, in addition to continuing to react to input stimulus as before, controls the device outputs. The two modes are successively achieved without requiring special external connections or special control commands. The test circuitry of the device is, therefore, essentially transparent unless specifically utilized, allowing the device to be used in systems which are not designed to utilize the test feature of the device as well as in those systems which do.

Method and apparatus for enabling and disabling a test mode of operation of an electronic memory device without additional interconnects or commands

A method and apparatus allows adapting a standard flying prober system to manually or automatically determine the likelihood of error free probability of test point targets on Printed Circuit Assemblies (PCA's) which may have significant planarity irregularities. The method and apparatus provides a corrective function allowing error free probing of test target points on PCA's having planarity irregularities which otherwise make them impractical to test. The method and apparatus involves utilizing the camera system typically provided with a flying prober system and an auxiliary sighting system each having different optical axis angles, the use of which allows determination of height values.

Method and apparatus for adapting a standard flying prober system for reliable testing of printed circuit assemblies

A method and apparatus allows adapting a standard flying prober system to probe test point targets on Printed Circuit Assemblies (PCAs) having irregularities in their planarity. The method and apparatus involves positioning a camera utilized by the prober system to predetermined offset positions relative to previously established test and/or other points for sets of images. Each set of images is processed by determining offsets in coordinates needed to align the images in a predetermined manner. The offsets for each measured point are translated into actual height values to be used during subsequent testing of a PCA.

Method and apparatus for enabling reliable testing of printed circuit assemblies using a standard flying prober system

The disc brake cooling system for a vehicle with hydraulic brakes has a sealed circular cooling system employing a piston pump which produces a very rapid flow of brake fluid through the brake lines and calipers constantly during non-braking of the vehicle. After braking, the constant rapid flow of the fluid cools the temperature of the fluid, and hence of the brakes, over the course of the rapid circular motion through the system so as to prevent boiling of the fluid.

Disc brake cooling system employing high speed piston pump

A method and apparatus provides an analog mode of operation of a standard test access bus interface based on a standard boundary scan architecture which is limited to use of digital signals. Circuits are included in the interface which enable the sharing of control paths at separate time intervals defined under instruction control for processing analog and digital signals thereby providing a hybrid capability without any increase in the number of lines required by the interface.

Boundary scan architecture analog extension with direct connections

An ESD protection system which shields PCAs during the assembly process comprises transportable support means for holding an ESD bag in a predetermined position which is convenient both for the insertion and extraction of a PCA(s) and for observing stored PCA(s), thus ensuring proper handling. The system has first and second attachment means for attaching the ESD bag to the frame and for holding papers associated with the PCA(s) outside the ESD bag and for providing the weight necessary for maintaining a sealing fold in the bag whenever the PCA(s) are enclosed therein. The transportable support means is a frame which is constructed to mate with a rack designed for accommodating a plurality of frames. When so mated, the rack provides the desired level of stability and orderly positioning of a desired number of frames spaced apart such that the ESD bags attached to the frames may be easily observed for correct loading, closure and paperwork processing. When not mated with the rack, the frame and all attachments may be transported with essentially the same convenience as transporting an ESD bag containing a PCA.

Electrostatic discharge (ESD) protection system for shielding a printed

A software implemented control mechanism is used in a test system for assigning unique pre-established electronic addresses which are to be written into the memory elements of printed circuit boards during the manufacture thereof. Each PCB is previously encoded with a scannable board serial number label, and the test system includes a processing unit and a memory configured for storing test software for testing PCBs. The control mechanism is incorporated into the test software which when installed into the test system configures the system's memory for assigning electronic addresses. The control mechanism includes first and second sets of tables containing entries which define the ranges of valid serial numbers and preallocated electronic addresses. A control element within the control mechanism invokes a number of offset computation subroutines which generates an offset value derived from the serial number read from the PCB being processed defining the relative position of the serial number as determined by entry values contained in the first set of tables. The control element provides the received offset value to a number of effective address subroutines which it invokes to select a valid unique electronic address value contained in the ranges of pre-established electronic addresses defined by the entry values contained in the second set of tables.

System and mechanism for assigning pre-established electronic addresses

A method and apparatus provides improved modes of operation of a standard test bus based on a standard boundary scan architecture which minimizes the number of bits required to be serially scanned into the controllers of the various devices connected to the bus by temporarily disabling scan paths not required to be utilized. Means for continuously verifying the inoperative state of test logic and for diagnosing test logic faults are also described.

Boundary scan architecture extension

A method and apparatus provides an analog mode of operation of a standard test access bus interface based on a standard Boundary Scan architecture which is limited to use of digital signals. Circuits are included in the interface which enable this sharing of data paths at separate time intervals defined under instruction control for processing analog and digital signals thereby providing a hybrid capability without any increase in the number of lines required by the interface.

Boundary scan architecture analog extension

A 'U' shaped unitary bracket is arranged for mounting about a forward edge of a window sill utilizing an adhesive strip mounted to a bottom surface of a first plate extending beyond an underlying parallel second plate. Connector fasteners are orthogonally directed through the second plate for securement to a bottom surface of the window sill. A modification of the invention includes a window box structure mounted to a connecting web of the first and second plates, with the window box including a rear wall mounting a plurality of sockets in a parallel relationship relative to the second plate utilizing threaded extender rods arranged for projection and in engagement with a rearwardly oriented vertical wall surface to align the window sill box relative to the associated window. A further modification of the invention includes an irrigation conduit structure positioned in an adjustable relationship overlying the window box for the continuous directing of irrigation fluid into the window box structure.

Window sill extension apparatus

A memory system containing groups of random access memory (RAM) devices further includes apparatus for distributing input memory addresses so diffused so as to cause the selection of different relative physical cell locations within each RAM device being accessed to provide a single word of information.

Method of organizing a memory for fault tolerance

A system provides for the testing of components which connect to one or more of programmable logic devices (PLDs), each of which is organized in a predetermined manner. Each PLD includes a plurality of programmable logic sections, each of which connect to I/O pins through driver and receiver circuits. An available section includes programmed means for causing its driver circuit to force the I/O pin to a first logic level when made operational. The other sections each include programmed means for connecting their associated driver circuits to be controlled by signals applied to the receiver circuit of the available section. During testing, means are externally applied to the I/O pin of the available section which drive the pin from the first logic level to a second logic level. This causes the receiver circuit to apply signals which inhibit the driver circuits of the remaining sections from applying signals to their I/O pins thereby enabling the testing of components which connect to these I/O pins without interference.

Method of organizing programmable logic array devices for board

An electronic assembly is made up of a number of electronic components. Each of the electronic components having a means for putting the component in a quiescent state while the remaining components are in a functional state, thereby enabling the testing of individual components without disassembly.

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South Boston, MA, United States of America

Robert J Russell