Intel Corporation

Intel Corportion

Robert J Riesenman

James M Dodd

Michael W Williams

David J Harriman

Brian K Langendorf

Eric C Samson

Michael N Derr

Brain K Langendorf

Hou-Sheng Lin

An embodiment may be an apparatus comprising a link coupled with a memory, and circuitry coupled with the link to calculate the amount of memory access idle time, determine if memory access idle time is sufficient to change to a self-refresh state, and change to a self-refresh state based on memory access idle time without explicit notification from a processor regarding the processor power state. Another embodiment may be a method for memory to enter self-refresh comprising calculating the amount of memory access idle time, determining if memory access idle time is sufficient to change to a self-refresh state, and changing to a self-refresh state based on memory access idle time without explicit notification from a processor regarding the processor power state. Various other embodiments systems, methods, machine readable mediums and apparatuses may provide similar functionality to these exemplary embodiments.

Mechanism for self refresh during advanced configuration and power interface (ACPI) standard C0 power state

A memory controller or other device may be programmed with a data mask mapping scheme. A selection device within the memory controller may be set with the data mask mapping scheme between data and a data mask. In one embodiment, a storage device may be included and programmed with the data mask mapping scheme.

Mapping data masks in hardware by controller programming

A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a location in memory. In still another embodiment, the data mask map is determined through an algorithm.

Obtaining data mask mapping information

A method and apparatus for high throughput multiplexing of data is described. It includes a circuit including: A first multiplexer having an output, a first input, a second input, and a selector. A second multiplexer having an output, a first input, a second input, and a selector, the output of the second multiplexer coupled to the first input of the first multiplexer. A third multiplexer having an output, a first input, a second input, and a selector, the output of the third multiplexer coupled to the second input of the first multiplexer; and the selector of the first multiplexer to select an input with a stable signal.

Method and apparatus for high throughput multiplexing of data

Methods and devices for a memory system are disclosed. A digital memory device can receive power-down commands during the pendency of an active-mode command such as a burst read or write, that is, &ldquo;early&rdquo;. The device shuts down some circuitry, such as address and command registers, immediately upon receipt of the early power-down command. Other device components, e.g., those involved in servicing the burst read or write, remain active at least until their portion of the command has been completed. In some embodiments, the early power-down command can be issued concurrently with an active-mode command as an option to that command, freeing a memory controller from having to schedule and issue power-down commands separately. Significant power savings, as compared to those obtained with prior-art memory device power-down modes, are possible.

Early power-down digital memory device and method

A combination precharge/activate command is utilized in order to make more efficient use of a command bus between a memory controller and a system memory. Upon receiving a precharge/activate command from the memory controller, the system memory makes a determination as to how to interpret the command depending on a page status. For an open page, the precharge/activate command is treated as a precharge command and then the system memory performs an activate with proper command timing using address and bank given during precharge/activate command. For a closed page, the precharge/activate command is treated as an activate command.

Implied precharge and posted activate command to reduce command bandwidth

One embodiment of the present invention is a PCI bus target device. The PCI bus target device includes a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit is configured to determine whether the PCI bus target device is the target of a first transaction initiated by a first PCI bus master device. The second circuit is configured to determine whether the PCI bus target device is ready to complete the first transaction. The third circuit is configured to determine whether a second PCI bus master device is ready to initiate a second transaction. The fourth circuit is configured to terminate the first transaction if the PCI bus target device is the target of the first transaction and is not ready to complete the first transaction and the second PCI bus master device is ready to initiate the second transaction.

Method and apparatus for terminating a bus transaction if the target is not ready

A system and method is provided for enhancing the efficiency with which commands from and initiating device to a resource are processed by the resource. The system includes a command queue, a plurality of command reorder slots coupled to the command queue, and command selection logic coupled to the resource and the command reorder slots. Commands ready for processing are loaded into the command reorder slots, and the command selection logic applies an efficiency criterion to the loaded commands. A command meeting the efficiency criterion is transferred to the resource for processing. The system may also include response reordering logic, which is coupled to the command reorder logic. The response reorder logic returns to original command order data provided in response to reorder read commands.

System for issuing a command to a memory having a reorder module for

A method and apparatus for fencing the execution of commands. A fence command and an executable command are received in succession. The executable command is enqueued in a first queue together with an indication that the executable command succeeded the fence command. A synchronization value is enqueued in a second queue. The executable command is then delayed from being dequeued from the first queue until the synchronization value is advanced to the head of the second queue.

System for delaying dequeue of commands received prior to fence command

A method of issuing a data retrieval command to a re-order unit in a bus bridge is described. The method requires maintaining an indication of the available (or unreserved) capacity in a data buffer into which a data package is received from a memory resource in response to a data retrieval command. Data packages are furthermore dispatched, relative to other data packages, in the order in which a corresponding data retrieval command is issued from a requesting device. The size of a data package requested by each data retrieval command is determined prior to issuance thereof to the re-order unit. The size of each data package is then compared to the then available capacity in the data buffer, and the relevant data retrieval command is only issued to the re-order unit if the available capacity in the data buffer is sufficient to accommodate the data package requested by the relevant data retrieval command.

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Sacramento, CA, United States of America

Robert J Riesenman