Honeywell International Inc.

Robert J Quirk

William Ray Hancock

Larry James Miller

Paul A Fisher

Panagiotis Papadatos

A method of ensuring high integrity of a processor is provided. The method includes executing sets of sequential instructions, each execution being based on a unique initial value, generating a computed final value responsive to each execution of a set of sequential instructions, and sending computed values to a monitoring portion of a high integrity processor monitor system responsive to the generating for each execution of the set of sequential instructions. The execution of the sets of sequential instructions tests pertinent addressing modes, operand sizes, and instruction side-effects for each instruction tested in a monitored central processing unit.

High integrity processor monitor

A system for detecting cursor interference includes a graphics engine configured to generate graphics information; a first evaluation unit coupled to the graphics engine and configured to evaluate the graphics information; a cursor generation unit coupled to the graphics engine and configured to generate cursor information, the cursor generator further configured to merge the cursor information and the graphics information into merged information; a second evaluation unit coupled to the cursor generation unit and configured to evaluate the merged information; and a display device coupled to the cursor generation unit and configured to display the merged information based on the evaluations of the graphics information and the merged information.

Systems and methods for detecting cursor interference in visual displays

In one embodiment of the present invention, a system for displaying images in at least one display window on a display unit includes a display processor configured to generate graphics commands from a received input. A graphics processing unit is coupled to the display processor and includes rendering engine configured to generate graphic data from the graphics commands, an internal memory coupled to the rendering engine, and a general purpose I/O coupled to the rendering engine and configured to transmit messages from the graphics processing unit. A graphics logic device is coupled to the graphics processing unit. The graphics logic device is configured to initiate a transfer of graphic data for an update of a display window from the internal memory to the display unit upon receipt of a message indicative of an available update to the display window. An external memory is coupled to the graphics logic device and the external memory is configured to supply graphic data to the display window when the update of the display unit is not available and to store the update of the display window when the display window receives the update from the internal memory.

Method and system for an external front buffer for a graphical system

An apparatus includes a rendering engine to render a foreground of an image. The apparatus also includes a logic, separate from the rendering engine, to merge at least one background color with the foreground of the image.

Background rendering of images

A system which utilizes two buffers of dual-port memory to seamlessly display video frames on a raster scanned video display device. Dual port memory is organized into two alternate memory banks, each having sufficient capacity to buffer a full frame of video data. As long as the display memory write and read addresses are sufficiently separated by a predetermined number of lines, video data is written and read using alternate banks of memory for each frame. When the write and read addresses are closer than a predetermined number of lines, the video data already stored in a given bank of memory is re-read. After the write and read addresses are again sufficiently separated, video data is again written and read using alternate banks of memory.

System for dual buffering of asynchronous input to dual port memory for a raster scanned display

A system which utilizes dual-port memory to seamlessly display video frames on a raster scanned display device. Dual port memory is partitioned into a 'single frame buffer' having sufficient capacity to buffer a full video frame, and an 'extension buffer' which is a contiguous extension of the single frame buffer. The two sections together comprise an &lsquo;extended buffer&rsquo;. As long as the video memory write and read addresses are sufficiently separated by a predetermined number of lines, video data is written and read using the single frame buffer for each frame. When the write and read addresses are closer than a predetermined number of lines, the incoming video data for the next several new frames is written using the &lsquo;extended&rsquo; buffer, and also read therefrom. After the write and read addresses are again sufficiently separated, video data is written and read using only the single frame buffer.

Growing community of inventors

Peoria, AZ, United States of America

Robert J Quirk