Integrated Device Technology, Inc.

Townsend and Townsend and Crew Llp

Other

Intergraph Corporation

Sun Microsystems, Inc.

Oracle America, Inc.

National Semiconductor Corporation

Intellectual Ventures I LLC

Townsend and Townsend Khourie and Crew

Fairchild Semiconductor Corporation

Netlogic Microsystems, Inc

Hyundai Electronics America, Inc.

Robert J Proebsting

Robert J Drost

Ronald Ho

Kee W Park

Scott Yu-Fan Chu

David J Pilling

Alex Chow

William H Herndon

Cesar A Talledo

Arlene Proebsting, Legal Representative

Steven R Boyle

William L Devanney

Robert J Bosnyak

Michael J Miller

Scott M Fairbanks

Mark W Baumann

Raymond A Heald

Roland T Knaack

Bruce Lorenz Chin

Hyunsoo Sim

An apparatus and system associated with memory are disclosed herein. In various embodiments, an apparatus may include first circuitry to determine a number of queued pending refresh requests for a memory bank based on a comparison of a count from a refresh-request counter to a count from a refresh-address counter; and second circuitry to set a refresh flag in response to a determination that the number of queued pending refresh requests exceeds a predetermined number. Other embodiments may be disclosed and/or claimed.

Refresh request queuing circuitry

An apparatus and system associated with memory are disclosed herein. In various embodiments, an apparatus may include first circuitry configured to queue pending refresh requests for a plurality of memory banks; and second circuitry coupled to the first circuitry and configured to set a refresh flag in response to a determination that a number of queued pending refresh requests for a memory bank from the plurality of memory banks exceeds a predetermined number. Other embodiments may be disclosed and/or claimed.

Concurrent memory bank access and refresh request queuing

One embodiment of the present invention provides a system that facilitates proximity communication. This system includes a circuit containing a bootstrap transistor and a pass-gate transistor, where the drain of the bootstrap transistor is coupled to the gate of the pass-gate transistor. Note that a first coupling capacitance exists between the source of the pass-gate transistor and the drain of the bootstrap transistor and a second coupling capacitance exists between the drain of the pass-gate transistor and the drain of the bootstrap transistor. During operation, the gate and the source of the bootstrap transistor are coupled to a high voltage, thereby causing an intermediate voltage at the drain of the bootstrap transistor. When the source of the pass-gate transistor transitions to a high voltage, the first coupling capacitance and the second coupling capacitance boost the voltage at the gate of the pass-gate transistor higher than the high voltage, thereby enabling the high voltage at the source of the pass-gate transistor to pass to the drain of the pass-gate transistor.

Circuit that facilitates proximity communication

One embodiment of the present invention provides a system that facilitates reducing the power needed for proximity communication. This system includes an integrated circuit with an array of transmission pads that transmit signals using proximity communication. This array is comprised of a set of macropads, where each given macropad is comprised of a set of micropads that can be configured to transmit a signal. A steering fabric routes signals to and within macropads, such that a subset of the micropads in the array can be configured to transmit the signal to a receiving component. Each macropad receives a limited number of input signals, with the steering fabric routing input signals to the micropads of the macropads. By limiting the number of input signals that are routed to the micropads of the macropads, the steering fabric eliminates redundant steering configurations for the array and reduces the power needed to transmit the signal.

Steering fabric that facilitates reducing power use for proximity communication

A method for calibrating an offset voltage of an amplifier used to amplify capacitively coupled communication signals is described. During this process, a common voltage is applied to one or more inputs to the amplifier. Next, an output of the amplifier is iteratively, measured, and charge is applied to the one or more inputs until the offset voltage is less than a pre-determined value. Note that applying the charge may involve applying a sequence of one or more charge pulses.

Offset cancellation in a capacitively coupled amplifier

One embodiment of the present invention provides a system that facilitates reducing the power needed for proximity communication. This system includes an integrated circuit with an array of transmission pads that transmit a signal using proximity communication. A layer of fill metal is located in proximity to this array of transmission pads, wherein the layer of fill metal is 'floating' (e.g., not connected to any signal). Leaving this layer of fill metal floating reduces the parasitic capacitance for the array of transmission pads, which can reduce the amount of power needed to transmit the signal.

Using floating fill metal to reduce power use for proximity communication

Content addressable memory (CAM) devices use both hard and soft priority techniques to allocate entries of different priority therein. The priorities of multiple CAM array blocks within the CAM device may be programmed before or as entries are loaded therein and may be reprogrammed during operation as the allocation of entries within the CAM device changes. The allocation of entries may change in response to additions or deletions of entries or as entries are reprioritized. The CAM devices include preferred priority resolution circuits that can resolve competing soft and hard priorities between multiple hit signals that are generated in response to a search operation. Such hit signals may be active to reflect the presence of at least one matching entry within a CAM array block. The resolution of which active hit signal has the highest overall priority among many can be used to facilitate the identification of the location (e.g., array address and row address) of a highest priority matching entry within the entire CAM device. A priority resolution circuit may also resolve competing hard priorities between two or more active hit signals having equivalent soft priority. This aspect of the priority resolution circuit is provided so that an active hit signal having a highest overall priority can be resolved whenever multiple CAM array blocks having the same soft priority are detected as having matching entries therein during a search operation.

Content addressable memory (CAM) devices having soft priority resolution circuits therein and methods of operating same

A dynamic random access memory integrated circuit and method includes internal refresh control and an array configured to receive read and write access requests having priority over pending refresh requests, wherein refresh requests are queueable and retired on clock cycles not requiring an access of the array and complete in one clock cycle. No on-board cache memory is required. A method includes: determining within the circuit when one of the banks of the array requires a refresh, prioritizing read and write access requests over pending refresh requests, read access requests initiating an access to the array without determining whether data is available from outside the array, and retiring within a clock cycle one pending refresh request to a bank when that bank has pending refresh requests and does not also require an access of the array on that clock cycle.

Integrated circuit random access memory capable of automatic internal refresh of memory array

A system that dynamically refreshes the inputs of a differential receiver. During operation, while a differential transmitter is not transmitting data, the system applies substantially equal voltages to the outputs of the differential transmitter so that the differential voltage on the outputs of the differential transmitter is substantially zero. The system then refreshes the inputs of an associated differential receiver by applying substantially equal voltages to the inputs of the differential receiver so that the differential voltage on the inputs of the differential receiver is substantially zero. The differential transmitter is coupled to the differential receiver through a DC blocking mechanism, which prevents a DC voltage on the differential transmitter from reaching the differential receiver.

Dynamic refreshed receiver for proximity communication

Content addressable memory devices include a bidirectional interface circuit configured to receive word line signals from a plurality of global word lines and pass match information from a selected one of a plurality of CAM arrays to the plurality of global word lines in response to detecting a match in the selected one of the plurality of CAM arrays.

Content addressable memory (CAM) devices having bidirectional interface circuits therein that support passing word line and match signals on global word lines

An integrated circuit delay device includes a digital delay line configured to provide a percent-of-clock period delay to a timing signal received at an input thereof, in response to a control signal. This control signal has a value that specifies a length of the delay. A delay line control circuit is also provided. The delay line control circuit is configured to generate the control signal by counting multiple cycles of a high frequency oscillator signal (e.g., ring oscillator signal) having a period less than the clock period, over a time interval having a duration greater than the clock period.

Integrated circuit systems and devices having high precision digital delay lines therein

One embodiment of the present invention provides a system that measures alignment between a first semiconductor die and a second semiconductor die. The system operates by applying a pattern of voltage signals to a two-dimensional array of conductive transmitter elements that form a transmitter array on the first semiconductor die. This transmitter array is positioned over a corresponding two-dimensional array of conductive receiver elements that form a receiver array on the second semiconductor die, whereby a voltage signal applied to a transmitter element induces a voltage signal in one or more receiver elements. The system amplifies voltage signals induced in receiver elements in the receiver array, and subsequently analyzes the amplified signals to determine an alignment between the first semiconductor die and the second semiconductor die.

Method and apparatus for using a capacitor array to measure alignment between system components

One embodiment of the present invention provides an arrangement of differential pairs of wires that carry differential signals across a semiconductor chip. In this arrangement, differential pairs of wires are organized within a set of parallel tracks on the semiconductor chip. Furthermore, differential pairs of wires are organized to be non-adjacent within the tracks. This means that each true wire is separated from its corresponding complement wire by at least one intervening wire in the set of parallel tracks, thereby reducing coupling capacitance between corresponding true and complement wires. Moreover, this arrangement may include one or more twisting structures, wherein a twisting structure twists a differential pair of wires so that the corresponding true and complement wires are interchanged within the set of parallel tracks.

Method and apparatus for routing differential signals across a semiconductor chip

A system that improves communications between capacitively coupled integrated circuit chips. The system operates by situating an interposer over capacitive communication pads on a first integrated circuit chip, wherein the interposer is made up of material that is anisotropic with respect to transmitting capacitive signals. A second integrated circuit chip is situated so that communication pads on the second integrated circuit chip are aligned to capacitively couple signals between the integrated circuit chips through the interposer. The increased dielectric permittivity caused by the interposer can improve capacitive coupling between opposing communication pads on the integrated circuit chips. The interposer can also reduce cross talk between communication pads on the first integrated circuit chip and pads adjacent to the opposing communication pads on the second integrated circuit chip.

Growing community of inventors

Sonora, CA, United States of America

Robert J Proebsting