Intel Corporation

Robert J Murray

Milo D Sprague

Rajesh Kumar

Paul D Madland

David K Li

Milo David Sprague

Helen Opie

Steve Curtis

A pulsed circuit topology to perform a memory array write operation. A write enable pulse width control circuit is responsive to a pulsed clock signal to generate a pulsed write enable signal and a write data path circuit is provided to output a write data signal. The write enable pulse width control circuit and the write data path circuit together control a write operation to a memory cell.

Pulsed circuit topology to perform a memory array write operation

A reset first latching mechanism comprises a pulse chopper circuit responsive to a pulsed signal to control initiation and termination of a reset pulse wherein a domino node is to be precharged in response to the reset pulse. The reset first latching mechanism also includes domino logic circuit responsive to an evaluate pulse at an input to evaluate at the domino node based on a logic function performed by the domino logic circuit. The reset pulse is timed such that the reset pulse is completed before the evaluate at the domino node occurs.

Reset first latching mechanism for pulsed circuit topologies

A pulsed circuit topology including a pulsed domino flip-flop. A circuit includes a domino logic gate having a domino output node responsive to input data during an evaluate pulse. Reset circuitry initiates and self-terminates a reset pulse during which the domino output node is precharged. A latch responsive to a first pulsed clock input signal is provided to latch data indicated at the domino output node.

Pulsed circuit topology including a pulsed, domino flip-flop

A microprocessor includes a register file that contains registers for storing pieces of data for use by execution units that receive the pieces of data through source ports. A bypass cache includes data registers into which pieces of data from the execution units are written. Data can be written to and read from the bypass cache in fewer clocks cycles than it can be written to and read from the register file. A content addressable memory array (CAM) includes address registers into which destination addresses are written which correspond to the pieces of data in the data registers. In the case of a particular piece of data, the particular data register into which the piece of data is written and the particular address register into which the corresponding destination address is written is controlled by the position of a write pointer provided by a rotating write pointer unit. The CAM includes a comparators that compare the destination address with a source address. If there is a match, a read port is enabled which provides the piece of data in the corresponding data register to conductors leading to the source port. Multiplexers select between pieces of data in the register file and a pieces of data in the data registers of the bypass cache.

Multiported bypass cache in a bypass network

A method and apparatus for comparing two N-bit digital numbers. The N bits from the two numbers are inputs to a comparator. In addition, a parity bit from each number is an input to the comparator. Thus, the logical distance between any two numbers as seen by the comparator is at least two.

Comparator utilizing redundancy

The precharged bit lines of a memory array are provided with corresponding pass gate devices and a common complementary regulation and control circuitry to keep the precharged bit lines at a voltage below a first voltage and to counter-act any leakage to Vcc through a small current drain to a reference voltage. As a result, the voltage on the precharged bit lines are prevented from moving closer to Vcc, even during a prolonged idle period, and failure will not occur, when the memory cells are accessed again after the prolonged idle period.

Memory arrays with integrated bit line voltage stabilization circuitry

The present invention provides a latching mechanism for use in high-speed domino logic pipestages. The latching mechanism allows time borrowing across latch boundaries, provides sufficient hold time for the output to be sensed by the next stage, and provides a circuit configuration in which race conditions related to the latching mechanism have inherent positive margin. The latching mechanism of the present invention is applicable to fully self-resetting domino logic, globally resetting domino logic, or any combination thereof. The latching mechanism is a set dominant latch having its set input driven by the output of the last domino logic gate in a pipestage, and having its reset input driven by the output of the last domino logic gate in a pipestage ANDed with a delayed version of the pulsed clock that triggers the domino chain of the pipestage.

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Portland, OR, United States of America

Robert J Murray