Intel Corporation

Lsi Corporation

Agere Systems Inc.

Other

Avago Technologies General IP (singapore) Pte. Ltd.

Robert J Munoz

David Sonnier

Ben-Zion Friedman

Deepak Mital

Joseph A Manzella

Sarig Livne

Walter A Roper

Ned M Smith

Francesc Guim Bernat

Johanna M Swan

Adel A Elsherbini

Kshitij Arun Doshi

Shawna M Liff

Dmitri E Nikonov

Kapil Sood

Tanay Karnik

Katalin Klara Bartfai-Walcott

Gerald S Pasdast

Sanjay Bakshi

Krishna Bharath

William G Burroughs

Robert G Southworth

Mark A Bordogna

Julien Sebot

Thomas P Thomas

Neelam Chandwani

Ronen Aharon Hyatt

James T Clee

Narender R Vangati

Nevine Nassif

Kursad Kiziloglu

Vinoj Narayan Kumar

Michael C Rifani

Chih-Jen Chang

Carleton L Molnar

Yue Yang

Nilesh S Vora

Zhong Guo

Karl T Matis

Matthew D Sibilio

Partick Fleming

Nir Tiser

John Mark Matson

A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.

Fine-grained disaggregated server architecture

Methods and apparatus to execute a workload in an edge environment are disclosed. An example apparatus includes a node scheduler to accept a task from a workload scheduler, the task including a description of a workload and tokens, a workload executor to execute the workload, the node scheduler to access a result of execution of the workload and provide the result to the workload scheduler, and a controller to access the tokens and distribute at least one of the tokens to at least one provider, the provider to provide a resource to the apparatus to execute the workload.

Methods and apparatus to execute a workload in an edge environment

Embodiments may relate to a substrate for use in a system in package (SIP). The substrate may include a first couple to couple with a first component via a permanent couple such that the first component is communicatively coupled with a bridge. The substrate may further include a second couple to removably couple with an interposer such that the interposer is communicatively coupled with the bridge via a communicative couple. Other embodiments may be described or claimed.

Removable interposer

Apparatuses and methods for managing jitter resulting from processing through a network interface pipeline are disclosed. In embodiments, a network traffic scheduler annotates packets to be transmitted over a bandwidth-limited network connection with time relationship information to ensure downstream bandwidth limitations are not violated. Following processing through a network interface pipeline, a jitter shaper inspects the annotated time relationship information and pipeline-imposed delays and, by imposing a variable delay, reestablishes bandwidth-complaint time relationships based upon the annotated time relationship information and configured tolerances.

Shaping of post-scheduling network pipeline jitter

Techniques to schedule transmission of a packet from a computing platform include calculating adjustments to portions of the packet to cause corrections to at least one portion of the packet. An adjustment to a scheduled transmission of the packet is made based on the corrections.

Techniques for packet transmit scheduling

Described embodiments process data packets received by a switch coupled to a network processor. The switch determines whether one or more rules for classifying and processing the received packet are stored in an internal classification database of the switch. If one or more rules are stored in the internal database, the switch updates statistics corresponding to each of the rules and classifies and processes the received packet in accordance with the rules. If no associated rules are stored in the internal database, the switch tags the received packet with metadata and forwards the packet to the network processor. The network processor determines one or more rules for classifying and processing the forwarded packet in a classification database of the network processor and updates statistics corresponding to each rule. The network processor classifies and processes the packet in accordance with the rules and updates the internal database of the switch.

Hierarchical self-organizing classification processing in a network switch

Described embodiments process data packets received that include a source address and at least one destination address. If the destination address is stored in a memory of an I/O adapter, the received data packet is processed in accordance with bridging rules associated with each destination address stored in the I/O adapter memory. If the destination address is not stored in the I/O adapter memory, the I/O adapter sends a task message to a processor to determine whether the destination address is stored in an address table stored in a shared memory of the network processor. The I/O adapter memory has lower access latency than the address table. If the destination address is stored in the address table, the received data packet is processed in accordance with bridging rules stored in the address table and the bridging rules stored in the I/O adapter memory are updated.

Address learning and aging for network bridging in a network processor

Described embodiments process data packets received by a network switch coupled to an external buffering device. The network switch determines a queue of an internal buffer of the network switch associated with a flow of the received packet and determines whether the received packet should be forwarded to the external buffering device. If the received packet should be forwarded to the external buffering device, the network switch sets an external buffering active indicator indicating that the network switch is in an external buffering mode for the flow, tags the received packet with metadata, and forwards the packet to the external buffering device. The external buffering device stores the forwarded packet in a queue of a memory of the external buffering device corresponding to the tagged metadata of the forwarded packet. The network switch processes packets stored in the internal buffer of the network switch.

Network switch with external buffering via looparound path

Described embodiments provide a network processor having a hardware accelerator that identifies a received packet and, based on a flow identification associated with the received packet, might pre-fetch pre-established portions of data from the received packet into local data memory (e.g., local data cache) for processing by a general purpose processor core. In addition to the packet data, the software necessary for the general-purpose processor core to process the data might also be pre-fetched into local instruction memory (e.g., local instruction cache). The flow identification might be used to select different portions of the packet and different software to be pre-fetched.

Packet data processor in a communications processor architecture

A multiprocessor system or a system of hardware accelerators is provided to reduce cache ping-ponging and to provide improved single producer single consumer (SPSC) queues and methods. The systems are configured for specifying separate cache attributes for inner (e.g., local) cache and outer (e.g., shared) cache for promoting lower system overhead. Separate cache attributes are specified such that shared variables are cacheable only in a cache level shared by multiple processors.

System and method for providing cache-aware lightweight producer consumer queues

The apparatus for producing a pulsing flow of fluids to a fluid line including a housing having first, second and third passages. The first passage communicates with a source of compressed gas and a first conduit, communicating with a solvent liquid source, and passes through the housing. A narrowed transverse dimension between the conduit and the inner chamber of the housing creates a pulsing delivery of fluids from the gas and liquid sources.

Fluid pulse generator for cleaning passageways

Described embodiments provide a system having a plurality of processor cores and common memory in direct communication with the cores. A source processing core communicates with a task destination core by generating a task message for the task destination core. The task source core transmits the task message directly to a receiving processing core adjacent to the task source core. If the receiving processing core is not the task destination core, the receiving processing core passes the task message unchanged to a processing core adjacent the receiving processing core. If the receiving processing core is the task destination core, the task destination core processes the message.

Network communications processor architecture

Described embodiments provide for a reassembly system for processing an asynchronous transfer mode (ATM) cell of data into an ATM adaptation layer (AAL) packet. A preprocessor module identifies a first conversation identification of one or more minipackets in the ATM cell, and reassembles the one or more minipackets having the first conversation identification into a portion of the AAL packet. A preprocessor determines if a trigger has occurred. In response to a trigger, the preprocessor sends a portion of the reassembled minipackets having the first conversation identification to a destination processor.

Packet reassembly processing

Described embodiments provide a system having at least two network processors that each have a plurality of processing modules. The processing modules process a packet in a task pipeline by transmitting task messages to other processing modules on a task ring, the task messages related to desired processing of the packet. A series of tasks within a network processor may result in no processing or reduced processing for certain processing modules creating a virtual pipeline depending on the packet received by the network processor. At least two of the network processors communicate tasks. This communication allows ter the extension of the virtual pipeline of or IC network processor to at least two network processors.

Sharing of internal pipeline resources of a network processor with external devices

Described embodiments provide for processing received data packets into packet reassemblies for transmission as output packets of a network processor. A packet assembler determines an associated packet reassembly of data portions and enqueues an identifier for each data portion in an input queue corresponding to the packet reassembly associated with the data portion. A state data entry corresponding to each packet reassembly identifies whether the packet reassembly is actively processed by the packet assembler. Iteratively, until an eligible data portion is selected, the packet assembler selects a given data portion from a non-empty input queue for processing and determines if the selected data portion corresponds to a reassembly that is actively processed. If the reassembly is active, the packet assembler sets the selected data portion as ineligible for selection. Otherwise, the packet assembler selects the data portion for processing and modifies the packet reassembly based on the selected data portion.

Packet assembly module for multi-core, multi-thread network processors

Growing community of inventors

Round Rock, TX, United States of America

Robert J Munoz